דרושים » הנדסה » Architecture Engineer, Senior Staff

As a Senior RTL Verification Engineer, you will lead the verification of complex subsystems and architectural features within a next-generation, high-performance RISC‑V Application Processor. You will work closely with architecture, design, modeling, software, validation, and implementation teams to ensure first-pass silicon success while meeting aggressive performance, power, and area (PPA) targets.

In this role, you will drive verification strategy, methodology, and execution from specification through tape-out, providing technical leadership in the definition of scalable verification environments, coverage closure plans, and debug methodologies. You will be expected to independently own large verification domains, influence design and architecture decisions, and mentor junior engineers.

The ideal candidate has extensive experience in CPU or SoC verification, with strong expertise in one or more of the following areas: RISC‑V architecture, CPU microarchitecture, MMU, memory hierarchy, cache coherence, interconnects, and micro-controller verification.

Responsibilities

Lead verification efforts for complex CPU and SoC subsystems from architecture definition through tape-out.

Define comprehensive verification strategies, test plans, coverage models, and closure criteria.

Architect, develop, and maintain advanced UVM-based verification environments and reusable verification components.

Drive verification execution, including stimulus development, functional coverage closure, assertions, regressions, and debug.

Collaborate closely with architecture and design teams to review specifications, identify ambiguities, and ensure verifiability.

Develop constrained-random, directed, and scenario-based tests to validate functional correctness and corner cases.

Drive root-cause analysis and resolution of complex design and verification issues.

Define and implement verification methodologies that improve scalability, quality, and productivity across the project.

Work with software, modeling, performance, and validation teams to develop system-level verification solutions.

Analyze verification metrics and risks, proactively driving closure plans to achieve project milestones.

Mentor junior verification engineers and contribute to the technical growth of the team.

Contribute to DV methodology discussions and influence verification best practices across the organization.

We are seeking a seasoned Sr Staff Physical Design Engineer to provide technical leadership across full-chip and multi-die physical implementation on advanced TSMC FinFET nodes. You will define and own the backend design methodology, champion Agentic AI integration into the PD flow, and mentor engineers across the team while interfacing directly with foundry, EDA vendors, and executive stakeholders.

What You'll Do
Architect and own the full-chip physical design strategy: floorplanning, power delivery network (PDN), clock architecture, PnR, and timing closure
Define and drive backend methodology standards across the team for advanced node tapeouts (N5/N4P/N3)
Lead critical timing closure efforts - MCMM, OCV, advanced ECO strategies, and cross-corner sign-off
Oversee and guide signal integrity, power integrity, EM/IR, and reliability analysis for full-chip designs
Architect and lead the development of scalable PD flow infrastructure using Python and TCL - including automated regression, sign-off reporting, and run management systems
Champion the adoption of Agentic AI in the design flow - define use cases, evaluate tools, prototype autonomous agents for floorplan exploration, timing closure, and ECO automation
Lead cross-functional design reviews with DFT, verification, analog, and process engineering teams
Interface with TSMC, EDA vendors (Synopsys, Cadence, Siemens), and internal research teams to evaluate and adopt new methodologies
Mentor and technically guide junior and mid-level PD engineers across the organization

We are looking for a System Architect. The architect will work closely with R&D development groups, as well as other departments in the company including product marketing, customer success and CTO office.

The System Architect is a senior member of the companys R&D team.

The Architect is responsible for defining system requirements and architecture for the companys products. In this position, the primary focus will be on the company Security Product.

Defining system requirements for products and features:
Bridging the gap between Product Managements high level product requirements, the specific problem domain, and the capabilities and constraints of products and technologies
Writing specification documents that are clear and detailed enough for development and testing of the product by the R&D team
Provide technological guidance in his/hers areas of expertise for other teams in the company
Participate in long-term research in new technologies and problem domains
Provide high level designs for Proof of Concepts and customer projects
Support Presales, R&D and Customer Support with understanding customer/problem-domain related issues, in both presale & support contexts.
Main Roles & Responsibilities

Data collection and analytics

System definitions for big data collection, processing and analytics in the system.
Involved in defining and selecting big data technologies
Cloud solutions

System definitions for our cloud deployment solutions in both private cloud and public cloud.
Define PoCs for new cloud solutions
Explore new cloud technologies

We are seeking a motivated FPGA Engineer with up to 3 years of experience to join our hardware development team. In this role, you will contribute to the design, implementation, verification, and debugging of FPGA-based solutions for advanced digital systems. You will collaborate with architects, ASIC/SoC designers, firmware engineers, and verification teams to develop high-performance products from concept through deployment.

This position offers an excellent opportunity to gain hands-on experience with modern FPGA technologies, digital design methodologies, and complex microcontrollers in a collaborative engineering environment.

Key Responsibilities
Design and implement FPGA logic using Verilog and SystemVerilog.

Develop and maintain FPGA subsystems, IP blocks, and reference designs.

Participate in FPGA architecture discussions and design reviews.

Perform RTL simulation, debugging, and functional verification.

Support synthesis, place-and-route, timing closure, and implementation activities.

Develop and execute test plans for FPGA validation and bring-up.

Debug hardware and system-level issues in laboratory environments.

Integrate interfaces such as JTAG, AHB, DDR, etc.

Collaborate with software, firmware, and hardware teams throughout product development.

Document designs, verification results, and development procedures.

Support prototype development and system integration activities.

The position is responsible for the technical leadership as well as the team management of ATE test station development and automation SW infrastructure, from system architecture, test strategy, down to production. We are seeking a highly experienced professional with a strong background in RF, digital, and system-level testing, and with the ability to guide technical decisions, and mentor engineers on ATE methodologies, operation, and maintenance.


Team Responsibility
Design and develop Automated Test Equipment (ATE) for RF, digital, and mixed-signal products at board and system levels.
Technical definition and implementation of test strategies in collaboration with R&D, product engineering, and manufacturing teams.
ATE integration with software and firmware control as well as with automation systems.