The position is responsible for the technical leadership as well as the team management of ATE test station development and automation SW infrastructure, from system architecture, test strategy, down to production. We are seeking a highly experienced professional with a strong background in RF, digital, and system-level testing, and with the ability to guide technical decisions, and mentor engineers on ATE methodologies, operation, and maintenance.


Team Responsibility
Design and develop Automated Test Equipment (ATE) for RF, digital, and mixed-signal products at board and system levels.
Technical definition and implementation of test strategies in collaboration with R&D, product engineering, and manufacturing teams.
ATE integration with software and firmware control as well as with automation systems.

We are seeking a motivated FPGA Engineer with up to 3 years of experience to join our hardware development team. In this role, you will contribute to the design, implementation, verification, and debugging of FPGA-based solutions for advanced digital systems. You will collaborate with architects, ASIC/SoC designers, firmware engineers, and verification teams to develop high-performance products from concept through deployment.

This position offers an excellent opportunity to gain hands-on experience with modern FPGA technologies, digital design methodologies, and complex microcontrollers in a collaborative engineering environment.

Key Responsibilities
Design and implement FPGA logic using Verilog and SystemVerilog.

Develop and maintain FPGA subsystems, IP blocks, and reference designs.

Participate in FPGA architecture discussions and design reviews.

Perform RTL simulation, debugging, and functional verification.

Support synthesis, place-and-route, timing closure, and implementation activities.

Develop and execute test plans for FPGA validation and bring-up.

Debug hardware and system-level issues in laboratory environments.

Integrate interfaces such as JTAG, AHB, DDR, etc.

Collaborate with software, firmware, and hardware teams throughout product development.

Document designs, verification results, and development procedures.

Support prototype development and system integration activities.

you will define system and IP architectures, develop architectural models, and author technical specifications for a variety of high-performance, high-quality, low-power, world-class products.

You will

Define and drive architectures across multiple domains, spanning chip-level components, subsystems, and system-level workflows.

Translate product requirements into architectural specifications, features, and hardware/software execution models for implementation teams.

Lead cross-functional technical decisions, balancing functionality, performance, scalability, power, and implementation trade-offs.

We are seeking a seasoned Sr Staff Physical Design Engineer to provide technical leadership across full-chip and multi-die physical implementation on advanced TSMC FinFET nodes. You will define and own the backend design methodology, champion Agentic AI integration into the PD flow, and mentor engineers across the team while interfacing directly with foundry, EDA vendors, and executive stakeholders.

What You'll Do
Architect and own the full-chip physical design strategy: floorplanning, power delivery network (PDN), clock architecture, PnR, and timing closure
Define and drive backend methodology standards across the team for advanced node tapeouts (N5/N4P/N3)
Lead critical timing closure efforts - MCMM, OCV, advanced ECO strategies, and cross-corner sign-off
Oversee and guide signal integrity, power integrity, EM/IR, and reliability analysis for full-chip designs
Architect and lead the development of scalable PD flow infrastructure using Python and TCL - including automated regression, sign-off reporting, and run management systems
Champion the adoption of Agentic AI in the design flow - define use cases, evaluate tools, prototype autonomous agents for floorplan exploration, timing closure, and ECO automation
Lead cross-functional design reviews with DFT, verification, analog, and process engineering teams
Interface with TSMC, EDA vendors (Synopsys, Cadence, Siemens), and internal research teams to evaluate and adopt new methodologies
Mentor and technically guide junior and mid-level PD engineers across the organization