דרושים » הנדסה » senior mixed-signal analog cad engineer

perform physical layout for mixed-signal functions like pll's, high speed i/o circuits, serdes, general i/o's, esd structures designs in state-of-the-art sub-micron cmos finfet technologies using cadence tools
you will work with asic and mixed-signal engineers to customize designs for integration in vlsi products.
job duties will include floor planning, custom layout and verifying against design rules and schematics, em/ir analysis

we are looking for an experienced dft engineer to join an exceptional team of dft experts to develop the next generation dft technologies.
as a dft engineer at the networking group at our company, you will participate in definition and implementation of our dft technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches, nic and SOC product lines. we are working closely with a wide range of aspects - chip design, backend, verification and production testing. we are working on the most advanced technologies and sophisticated products, our dft solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for defining, coding and integrating sophisticated dft components into various projects and using state-of-the-art technologies.
as a member of our dft design team, you will participate in defining various dft features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.
strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

our company is looking for best-in-class physical design cad engineer to join our outstanding networking silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
you will be in charge of developing physical design, synthesis, sta and logic eq methodologies for implementation of networking chips and socs.
work closely with block owners. full chip sta engineers and project managers to assure high quality and timely convergence.
come up with unique and creative solutions to the state of the art physical design problems that are needed for our chips.
additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, p&r, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.

our company is at the forefront of ai-driven innovation in vlsi design automation. join us to shape the future of semiconductor design with cutting-edge ai tools and make a significant impact in a collaborative, high-performance environment. are you ready to push the boundaries of whats possible in vlsi cad? come be part of our pioneering team!
what you'll be doing:
you will be responsible for developing and integrating advanced cad solutions and automation flows using ai and Machine Learning for vlsi design, verification, and implementation.
work closely with design, verification, and cad teams to identify areas for improving vlsi workflows using advanced tools and methods.
research, prototype, and deploy ai-based algorithms.
develop and maintain scripts and automation infrastructure to enable seamless adoption of ai tools in the vlsi design process.
continuously review emerging ai technologies and methodologies to keep our cad environment up-to-date.
provide Technical Support and training to engineering teams on ai-enabled cad flows and best practices.

come join the team and see how you can make a lasting impact on the world.
what youll be doing:
analyze pcb designs for manufacturability (dfm) and assembly (dfa) and identify issues early in the design cycle.
collaborate with hardware, layout, and manufacturing teams to ensure design intent aligns with production capabilities.
use cad tools such as cadence allegro and siemens valor to review and optimize pcb layouts.
participate in design reviews and cross-functional meetings to address manufacturing constraints and improve design quality.
document and promote best practices and dfm/dfa guidelines across teams.
support root cause analysis and resolution of manufacturing issues during new product introduction.
stay current with industry standards and emerging pcb manufacturing technologies.

our company is hiring a senior, hands-on engineer to lead technical innovation in our design verification (dv) automation infrastructure. this role requires a strong design/verification background combined with a proactive approach - identifying inefficiencies, proposing creative solutions, and implementing them with high ownership and impact. you will directly influence how verification is performed across our next-generation networking chips, enabling more scalable, efficient, and robust flows for complex asics powering the ai revolution. 
what you'll be doing:
lead the development of advanced verification automation tools, regression flows, and debug infrastructure.
identify key challenges and inefficiencies in current dv methodologies and proactively propose and implement improvements.
work closely with dv engineers, design teams, and tool developers to ensure solutions are practical and impactful.
balance innovation with hands-on engagement in daily dv issues - keeping a strong connection to real-world challenges and support needs.
act as a technical leader within the team, driving discussions, mentoring peers, and crafting strategic directions for dv automation.

our company is looking for an experienced dft design engineer to join the dft design team and develop the next generation dft technologies.
as a design engineer in the dft design team at our company, you will participate in definition and implementation of our dft technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches, nic and SOC product lines. we are working closely with a wide range of aspects - chip design, backend, verification and production testing. we are working on the most advanced technologies and sophisticated products, our dft solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for defining, coding and integrating sophisticated dft components into various projects and using state-of-the-art technologies.
as a member of our dft design team, you will participate in defining various dft features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.
strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

our company has continuously reinvented itself over two decades. our invention of the gpu in 1999 sparked the growth of the pc gaming market, redefined modern computer graphics, and revolutionized parallel computing. more recently, gpu deep learning ignited modern ai - the next era of computing. our company is a learning machine that constantly evolves by adapting to new opportunities that are hard to seek, that only we can pursue, and that matter to the world. this is our lifes work, to amplify human creativity and intelligence. make the choice to join us today.
what youll be doing:
working closely with product design engineers, you'll perform pcb layout of high speed/high-density value-conscious pcbs for all business units at our company (gpu desktop, notebook, automotive, professional, data center, deep learning, and ai), all using cadence pcb design tools.
focus will be on the complete development of cad layout from symbol creation, floor planning, and detailed component placement, constraints management, with a concept of topology and signal/trace integrity.
you will be responsible for the design releases required generation of artwork files, odb++, and electronic pcb documentation.
your designs will need to follow si constraints, emi/rfi control and fcc, ul and european regulations, ipc specifications and nrc regulations.

our company has been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. its a unique legacy of innovation thats fueled by great technology-and amazing people. today, were tapping into the unlimited potential of ai to define the next era of computing. an era in which our gpu acts as the brains of computers, robots, and self-driving cars that can understand the world. doing whats never been done before takes vision, innovation, and the worlds best talent. as an employee, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. come join the team and see how you can make a lasting impact on the world.
at our networking, we are driven by innovation and excellence. our team in israel is looking for a dedicated chiplet layout owner to join us in defining the next era of ai's networking. this is an outstanding opportunity to work with innovative technology and collaborate with some of the most experienced minds in the industry. if you are ambitious, passionate about flawless design, and eager to make a lasting impact, this role is perfect for you!
what you'll be doing: be part of a cross-business-unit team and own the high-speed ip integration.
build a chiplet floorplan layout design from early assembly/planning through implementation and signoff.
work closely with partition owners and full chip sta engineers to assure high quality and timely convergence.
define and implement efficient, high-quality full chip/chiplet physical design tools, flows, and methodologies.
gain hands-on experience implementing the partition-level be design (rtl2gds).

our networking division is a leading supplier of innovative end-to-end infiniband and ethernet connectivity solutions and services for servers and Storage. we offer market-leading solutions that include adapter cards, switches, optical transceivers, cables, and software to support networking technologies. our products optimize data centre performance and deliver industry-leading bandwidth and scalability. in addition, we serve a wide range of sectors including high performance computing, enterprise, data centres, cloud computing. we are constantly reinventing ourselves to stay ahead of the market and bring ground-breaking products and services to the industry by using novel technologies. our products are focused on delivering the most optimized power - performance communication solutions for industries like ai, ml, cloud, media and entertainment. 
we are seeking experienced electrical engineers with a passion for system -level thinking and innovation in high-performance optical switch development. this role offers a unique opportunity to shape and deliver next-generation products that push the boundaries of high-speed optical communication.
what youll be doing:
leading and be the technical focal point to integration of system optical phy and CPO electrical subsystems, ensuring its performance.
hands on cross-disciplinary testing efforts and lab work, collaborating with system architecture, optics, silicon, thermal, mechanical, signal/power integrity, and software teams.
characterization and testing of optical links using lab equipment (e.g., oscilloscopes, ber testers, optical spectrum analyzers and simulation tools).
driving product scalability, working with internal partners-qualification teams to transition designs from prototype to high-volume production.
documentation and reporting of design specifications, TEST results, and performance metrics.