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26/03/2026
חברה חסויה
Location: Yokne`am
Job Type: Full Time
we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
perform advanced static timing analysis (sta) for hsio at chiplet and fc level.
running prime time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
identify convergence risks and work closely with physical design, rtl and dft teams, ensuring convergence throughout various project stages.
responsible for a full timing closer and quality approval from pre-layout sta model through signoff.
ai use for timing optimization and data analysis.
Requirements:
b.sc./ m.sc. in electrical engineering.
at least 5+ years of hands-on sta experience.
experience in prime time and signoff methodologies.
a great teammate who thrives in a collaborative environment.
ai tools orientation or alternatively a desire to learn.
ways to stand out from the crowd:
agentic frameworks.
ai prompting experience.
experience in Linux environments.
tcl, Python, shell scripting abilities.
experience with data collection and analysis.
This position is open to all candidates.
 
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26/03/2026
חברה חסויה
Location: Yokne`am
Job Type: Full Time
our team in israel is looking for a dedicated chiplet sta owner to join us in defining the next era of ai's networking. this is an outstanding opportunity to work with innovative technology and collaborate with some of the most experienced minds in the industry. if you are ambitious, passionate about flawless design, and eager to make a lasting impact, this role is perfect for you!
what you'll be doing:
perform advanced static timing analysis (sta) at chiplet and fc level.
running prime time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
identify convergence risks and work closely with physical design, rtl and dft teams, ensuring convergence throughout various project stages.
responsible for a full timing closer and quality approval from pre-layout sta model through signoff.
Requirements:
what we need to see:
b.sc./ m.sc. in electrical engineering.
at least 5+ years of hands-on sta experience.
experience in prime time and signoff methodologies.
excellent leadership capabilities.
ways to stand out from the crowd:
knowledge in physical design flows and methodologies (synthesis, pnr, dft designs).
trong background of prime time tool.
great teammate.
This position is open to all candidates.
 
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22/03/2026
חברה חסויה
Location: More than one
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:
You will be responsible for complex physical design unit designs, ensuring integration within our innovative builds.
We expect you to run, debug, and approve PnR and verification flows across multiple projects, ensuring strict adherence to our high standards.
You will perform physical design implementation, planning and optimization, contributing to the development of our groundbreaking chips.
Requirements:
What we need to see:
B.SC./ M.SC. in Electrical Engineering
You should have at least 5+ years of hands-on Physical Design 'Place and Route' experience, demonstrating your proven expertise.
A strong background in Physical Design methodology, including Synthesis, Floorplan, CTS and Routing, is necessary.
Sign-off stages experince such as , 'STA', 'PV', 'LEC' and 'EMIR'.
In-depth knowledge of advanced silicon process technologies.
Familiarity with physical build EDA tools, including Synopsys and Cadence.
A great teammate who thrives in a collaborative environment.
AI tools orientation or alternatively a desire to learn.

Ways to stand out from the crowd:
AI prompting experience.
Experience in Linux environments.
TCL, Python, shell scripting abilities.
Experience with data collection and analysis.
Understanding of the chip and die verification process.
This position is open to all candidates.
 
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26/03/2026
Location: Yokne`am
Job Type: Full Time
we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
you will be responsible for chip floorplan and pin placement, ensuring integration within our innovative builds.
we expect you to run, debug, and approve physical verification flows across multiple projects, ensuring strict adherence to our high standards.
you will perform physical layout implementation, planning and optimization, contributing to the development of our groundbreaking chips.
we are widely considered to be one of the technology worlds most desirable employers. we have some of the most forward-thinking people in the world working for us. are you a creative and autonomous engineer who loves a challenge? are you ready to become the engineer you always wanted to be? come and be part of the best physical design team in the industry!
Requirements:
b.sc./ m.sc. in electrical engineering
you should have at least 5+ years of hands-on layout experience, demonstrating your proven expertise.
a strong background in physical verification methodology, including erc, lvs and drc, is necessary.
in-depth knowledge of advanced silicon process technologies.
familiarity with physical build eda tools, including synopsys and cadence.
a great teammate who thrives in a collaborative environment.
ai tools orientation or alternatively a desire to learn.
ways to stand out from the crowd:
experience in Linux environments.
tcl, Python, shell scripting abilities.
experience with data collection and analysis
understanding of the chip and die verification process
This position is open to all candidates.
 
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26/03/2026
Location: Yokne`am
Job Type: Full Time
we are looking for best-in-class physical design power engineer to join our outstanding networking silicon power engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput, lowest latency and best power! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you will be doing:
power optimization of physical design, of blocks/top-level/fc under challenging constraints.
optimization involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.
power estimation and power modeling.
Requirements:
what we need to see:
b.sc./ m.sc. or equivalent experience in electrical engineering/computer engineering.
2+ years of experience in physical design and/or be power optimization aspects.
familiarity with physical design eda tools (such as synopsys, cadence, etc.).
knowledge in physical design flows and methodologies (pnr, sta, physical verification) is an advantage.
fe design experience is an advantage.
excellent problem-solving, partnership, and interpersonal skills.
our company has some of the most forward-thinking people in the world working for us. are you a creative and autonomous engineer who loves a challenge? are you ready to become the engineer you always wanted to be? come and be part of the best physical design team in the industry!
This position is open to all candidates.
 
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27/03/2026
Location: Yokne`am
Job Type: Full Time
we are now looking for best-in-class senior chip design Verification engineer to join our outstanding network adapter silicon group, developing the industry's best high-speed smart communication devices, data processing unit (dpu), delivering the highest throughput and lowest latency! come and take a significant part in verifying and designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company. 
what you'll be doing:
work in a verification team which develops some of the networking silicon core units.
build reference models, verify and simulate chip blocks/entities according to specifications under challenging constraints with high orientation to performance.
gain a strong understanding of chip micro-architecture and features, and develop the verification environments.
work closely with multiple teams within organizations such as architecture, micro- architecture, and fw.
Requirements:
what we need to see:
b.sc. or above in electrical engineering or computer engineering.
5+ years of validated experience.
professional verification experience, knowledge in advanced verification methodologies and tools.
a team player with excellent communication and interpersonal skills.
strong debugging, problem solving and analytical skills.
demonstrates deep understanding in design and verification logic.
self-motivated, ability to work independently and drive tasks to completion. 
ways to stand out from the crowd:
prior design or verification experience of high-speed interconnects, smart nic and/or SOC.
experience in developing verification environments in Specman and/or prior knowledge in verilog.
knowledge in network protocols.
This position is open to all candidates.
 
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27/03/2026
חברה חסויה
Location: Yokne`am
Job Type: Full Time
we are looking for best-in-class senior full-chip Verification engineer to join our networking silicon team. in this role, you will be responsible for the development and verification of our next-generation nics at the system level. you will contribute to the architecture of high-speed communication devices by driving full-chip verification execution for the networking solutions powering the worlds most advanced data centers, enjoy working in a meaningful, growing environment where you make a huge impact in a technology-focused company.
what youll be doing:
full-chip verification & execution: own complex system -level features by defining verification plans and driving the end-to-end execution.
system -level debug & analysis: gain a strong understanding of chip micro-architecture and features, investigate, debug, and resolve cross-block issues to guarantee feature correctness and compliance
cross-team collaboration: work closely with multiple teams within organizations such as architecture, u-arch, firmware and all units inside the nic
ai-enhanced development: accelerate development by leveraging cutting-edge ai coding tools and frameworks.
Requirements:
what we need to see:
electrical engineering b.sc. or computer engineering b.sc. graduate with high scores or equivalent experience
8+ years of experience in verification or hw simulation
strong debugging, problem solving and analytical skills
innovation mindset - a proactive approach to adopting new methodologies and coding tools to solve complex challenges
a team player with good communication and interpersonal skills
ways to stand out from the crowd:
prior design or verification experience of high-speed interconnects, smart nic and/or SOC
knowledge in network flows and protocols
This position is open to all candidates.
 
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26/03/2026
Location: Yokne`am
Job Type: Full Time
we are hiring a skilled senior dpu performance Validation engineer for our dpu product lines. this includes chip architecture performance characterization, debug, and validation across single-die and multi-die systems. working in the network silicon engineering group, you will be responsible for debugging, analyzing, and validating performance and functional behavior of current and future silicon devices. you will collaborate with chip design, verification, fw, and architecture teams to ensure successful product development with bold product cycles. the qualified candidate should be comfortable working in simulation and emulation environments, with strong skills in rtl-level debug, waveform analysis, and system -level performance root cause analysis.
what you will be doing:
learn and analyze system -level operation of dpus
debug and root-cause performance issues in pre-silicon environments, across rtl, waveform traces, and multi-die system simulations.
collaborate closely with design, verification, architecture, and performance modeling teams to isolate and fix issues.
develop and improve validation methodologies for performance experiments and data collection.
automate repetitive debug and validation tasks to scale coverage and efficiency.
Requirements:
b.sc. in electrical engineering, computer engineering, or equivalent
5+ years of experience in asic development/validation.
strong background in asic debug, including reading rtl, analyzing waveforms, and root-causing functional or performance issues.
hands-on experience with performance validation and analysis at the system level (die-level or multi-die systems).
proficiency with Python and C / C ++ in a Linux environment.
excellent interpersonal skills and ability to work optimally as part of a multi-functional team.
ways to stand out from the crowd:
shown expertise in performance modeling, traffic generation, or architecture studies.
experience with modern interconnects and protocols (e.g., pcie, ethernet, chi).
familiarity with emulation platforms (e.g., palladium, veloce, fpga prototyping).
passion for experimental work, data -driven validation, and creative problem solving.
This position is open to all candidates.
 
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22/03/2026
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are now looking for an Arch Simulation Manager to join our Networking team! As a Switch-Arch Simulation Manager in our Networking Business Unit, you will lead a team of highly skilled hardware engineers responsible for verifying the next generation of our cutting-edge Switch products. This is a unique opportunity to make a real impact at the heart of our AI and HPC revolution, while working in a fast-paced, innovative environment. You will be part of a passionate and experienced team using modern approaches to validate the performance requirements for the next generation of our networking products. Your work will influence key architectural decisions and help deliver world-class silicon solutions for data centers, high-performance computing, networking, and storage applications.

What Youll Be Doing:

Lead and grow a team of hardware verification engineers focused on Arch performance validation of complex digital designs.

Collaborate closely with Architecture, Design, DV teams to identify verification needs and drive closure.

Provide technical guidance, mentoring, and support to engineers in the team.

Own the planning and execution of simulation deliverables to ensure high quality and timely tapeouts.
Requirements:
What We Need to See:

BSc or MSc in Electrical/Computer Engineering, or Computer Science.

3+ years of managerial experience in a chip design or verification domain.

8+ overall years of overall industry experience in modeling, hardware verification, or RTL design.

Excellent leadership, problem-solving, and communication skills.

Ways to Stand Out from the Crowd:

Hands-on experience with modeling.

Networking and Switch specifically experience.

Background in developing modeling testbenches, regression environments, and CI/CD workflows

Managerial experience in chip design domain

A passion for recruiting , leading , mentoring engineers and building strong, collaborative teams.
This position is open to all candidates.
 
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27/03/2026
Location: Yokne`am
Job Type: Full Time
nvidia's new product introduction (npi) team is growing, and we're looking for a highly motivated and diligent engineering vendor manager to join us. in this critical role, you'll be responsible for the engineering management of our most strategic and technologically advanced suppliers, ensuring the highest quality and reliability of components for our groundbreaking products.
 
nvidia networking division is a leading supplier of innovative end-to-end nvlink, infiniband and ethernet connectivity solutions and services for servers and Storage. we offer market-leading solutions that include adapter cards, switches, cables, and software to support networking technologies. our products optimize data center performance, using nvidias ai solution and deliver industry-leading bandwidth and scalability. in addition, we serve a wide range of sectors, including high-performance computing, enterprise, data centers, cloud computing, Big Data, and web 2.0.
what you'll be doing:
lead engineering engagement with strategic and critical suppliers for new product introductions (npi) and ongoing production, identify potential risks, critical parameters, and areas for optimization
define and implement clear monitoring and documentation requirements for key process steps to ensure consistency and quality
establish comprehensive quality criteria and outgoing quality control (oqc) procedures at suppliers prior to shipment
monitor and analyze supplier yield data, production metrics, and quality performance to identify trends and drive corrective actions
collaborate closely with internal nvidia engineering teams (design, product, reliability, quality) to ensure supplier capabilities align with product requirements
drive continuous improvement initiatives at suppliers to enhance process control, yield, and overall product quality
conduct supplier technical audits and provide mentorship on standard processes in manufacturing and quality control
act as the primary technical interface between nvidia and strategic suppliers, resolving complex engineering challenges
Requirements:
what we need to see:
bachelor's or master's degree in electrical engineering, mechanical engineering, materials science, or a related technical field.
8+ years of relevant experience.
proven experience in engineering roles, with a significant portion focused on supplier management, manufacturing engineering, or np.
proven track record to understand complex manufacturing processes and identify critical control points.
strong background in quality methodologies (e.g., six sigma, fmea, spc). experience with yield analysis, data interpretation, and driving root cause analysis for technical issues.
excellent communication, interpersonal, and leadership skills to effectively collaborate with internal teams and external suppliers.
ability to travel internationally to supplier sites as needed.
ways to stand out from the crowd:
experience with advanced manufacturing technologies (e.g., advanced packaging, high-speed pcbs, electro-mechanical, mechanical, electrical, high speed io, etc.)
familiarity with npi processes in a fast-paced technology company
proven track record of driving significant quality or yield improvements at suppliers
experience with dfm (design for manufacturability) and dft (design for testability) principles
This position is open to all candidates.
 
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26/03/2026
Location: Yokne`am
Job Type: Full Time
looking for senior software program manager that will be responsible for software programs and projects. the pm should drive planning and execution of fw/sw projects while aligning with corporate priorities and constraints.
 a leading supplier of innovative end-to-end infiniband and ethernet connectivity solutions and services for servers and Storage. we offer best-in-class solutions that include adapter cards, switches, cables, and software to support networking technologies. our products optimize data center performance and deliver industry-leading bandwidth and scalability. in addition, we serve a wide range of markets including high-performance computing, enterprise, data centers, cloud computing, Big Data and web 2.0. we are constantly reinventing ourselves to stay ahead of the market and bring groundbreaking products and services to the industry. our product line is focusing on delivering the most optimized ethernet solutions for industries like media and entertainment as well as any other industry that can benefit from our datastream and tcp/ip acceleration. 
what you'll be doing:
you will manage the networking software programs for nvidia next generation ai  data centers 
responsible to coordinate between all project stakeholders such as marketing, engineering teams in il and around the world, operations, etc. from initial requirements definition through architectural stage, execution, and delivery.
develop and execute feature planning and prioritization of perception capabilities to meet the software programs' needs
identify risks, gaps, and bottlenecks in time, and find resolution with technical leaders and project management
work with product managers, architects, and engineers to ensure consistency with company strategy, commitments, and goals
Requirements:
what we need to see:
b.sc. or m.sc. in Computer Science, electrical engineering, or related field
expert with software project management methodologies and tools
8+ years experience in software project management or leadership
experience in software development over hardware/silicon products
teammate, independent, responsible, capable of multi-tasking, ability to drive people and tasks
excellent verbal and written communication skills with english proficiency
ability and willingness to work in a dynamic environment and flexible hours, with teams all over the world 
ways to stand out from the crowd:
technical orientation, including the ability to conduct technical discussions
experience with tools such as ms excel, ms project, power BI
networking background
experience in multiple groups coordination
familiarity with sw agile concept
if you're creative and autonomous, we want to hear from you! nvidia is committed to fostering a diverse work environment and is proud to be an equal opportunity employer. as we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
This position is open to all candidates.
 
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