Senior Product Engineer

26/03/2026

silicon quality and reliability engineer, google cloud

חברה חסויה

Location: Tel Aviv-Yafo and Haifa

Job Type: Full Time

in this role, you will help build socs by driving quality and reliability processes from the integrated circuit (ic) perspective. working with various cross-functional teams, you will develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute TEST plans. within the larger organization, you will collaborate with global hardware quality and reliability, silicon design, validation, and engineering teams. you will have an understanding of ic flows, wafer processing, testing, qualification, yield, reliability, and failure analysis.the ml, systems, & cloud ai (msca) organization at google designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define and lead qualification hardware and TEST developments in front of internal teams and external vendors.
define and execute silicon and package qualification activities (e.g., htol, elfr, esd/lu, b/hast, thb, etc.).
extract, manipulate, and analyze large volumes of data from silicon and package qualification programs (e.g., htol, elfr, esd, lu, uhast, tct, etc.), high volume mfg, and field returns to identify failure mechanisms, reliability trends, and opportunities for yield, quality, and reliability improvement.
own cross-functional investigation of ic quality and reliability issues to identify root causes and develop solutions (e.g., rma triage, analytics, failure analysis, etc.).
develop and implement physics-based statistical quality and reliability models (e.g., elf, tddb, nbti, hci, time zero failures, etc.) to predict silicon device failure mechanisms, degradation patterns, and lifetime behaviors.

Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, materials science, a related technical field, or equivalent practical experience.
2 years of experience in ic silicon quality or reliability.
experience in semiconductor cmos technology, device physics, failure mechanisms, and accelerated TEST methodologies.
experience in reliability modeling, data analytics, and statistics.
preferred qualifications:
experience in semiconductor reliability, manufacturing processes (e.g., fab, assembly, TEST ), or ic and packaging failure mechanisms and related failure analysis.
experience in data analytics, especially to identify commonalities and abnormalities.
knowledge of design-for-reliability guidelines and implementation techniques.
familiarity with TEST methods and hardware for silicon qualification (e.g., htol chambers, esd, lu, etc.).

This position is open to all candidates.

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26/03/2026

design technology co-optimization engineer

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

about the job
in this role, youll work to shape the future of ai/ml hardware acceleration. you will have an opportunity to drive cutting-edge tpu (tensor processing unit) technology that powers google's most demanding ai/ml applications. youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of google's tpu. you'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on tpu architecture and its integration within ai/ml-driven systems.
as a design technology co-optimization (dtco) engineer, you will bridge the gap between process technology and product architecture to define the next generation of datacenter-class silicon. you will be responsible for extracting maximum process entitlement by evaluating advanced logic nodes and emerging transistor architectures.in this role, you will conduct place and route experiments and sensitivity analyses to influence standard cell library architecture, metal stack definitions, and design rules. you will collaborate with foundry, ip, and architecture teams to identify power, performance, and area (ppa) bottlenecks and drive system technology co-optimization (stco) initiatives.your work will involve performing high-fidelity physical implementation sweeps, analyzing the impact of scaling boosters, and developing automated methodologies to quantify ppa gains. by navigating the trade-offs between process complexity and design performance, you will ensure googles hardware achieves efficiency and power density.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
execute high-fidelity place and route experiments to evaluate the ppa impact of advanced process features, library architectures, and design rule variations on datacenter-class ip.
drive design technology co-optimization by collaborating with foundries and internal technology teams to define optimal metal stacks, track he

דרישות:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, or a related field, or equivalent practical experience.
2 years of experience in physical design (rtl-to-gds) or technology development, focusing on advanced nodes (e.g., 7nm, 5nm, or below).
experience with industry-standard place and route (p&r) tools and static timing analysis (sta) tools.
experience in cmos device physics, finfet/nanosheet architectures, and the impact of layout parasitics on ppa.
experience in scripting and automation using tcl and Python (or PERL ) to manage design sweeps and data extraction.
preferred qualifications:
master's degree or phd in electrical engineering, computer engineering or Computer Science, with an emphasis on computer architecture.
experience in design technology co-optimization (dtco), including standard cell library characterization, metal stack optimization, and evaluation of scaling boosters (e.g., backside power delivery).
experience working with major foundry technology files (pdks) and interpreting design rule manuals (drm) to guide physical im המשרה מיועדת לנשים ולגברים כאחד.

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26/03/2026

senior silicon dft lead

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as the design for TEST (dft) engineer lead, you will play a crucial role in dft architecture and dft design, and support devices to production. you will be responsible for providing technical leadership in dft, developing flows, automation, and methodology, planning dft activities, tracking the dft quality throughout the project life-cycle, and providing sign-off dft to tapeout.the ai and infrastructure team is redefining whats possible. we empower our company customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers, our company cloud customers, and billions of our company users worldwide. we're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our company cloud, our company global networking, data center operations, systems research, and much more.
responsibilities
lead and execute dft activities in the design, implementation, and verification solutions for application-specific integrated circuits (asic).
develop dft strategy and architecture, including hierarchical dft, memory built-in self TEST (mbist), and automatic TEST pattern generation (atpg).
work with other engineering teams (e.g., design, verification, physical design) to ensure that dft requirements are met and mutual dependencies are managed.
manage a dft team planning, deliverables, and provide technical mentoring and guidance.
lead dft execution of a silicon project, planning, execution, tracking, quality, and signoff.

Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, or a related field, or equivalent practical experience.
8 years of experience in design for TEST from dft architecture to post silicon production support.
4 years of experience with people management.
experience with dft design and verification for multiple projects, dft specification, definition, architecture, and insertion.
experience with dft techniques and common industry tools, dft and physical design flows, and dft verification flow.
experience in leading dft activities throughout the whole asic development flow.
preferred qualifications:
master's degree in electrical engineering or a related field.
experience in post-silicon debug, TEST or product engineering.
experience in jtag and ijtag protocols and architectures.
experience in SOC cycles, silicon bring-up, and silicon debug activities.
knowledge of fault modeling techniques.

This position is open to all candidates.

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8592844

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26/03/2026

senior manager, software verification

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

seeking a dynamic and highly motivated senior Software manager to lead our software verification and automation for doca networking sdk. we are looking for a candidate who can excel in a sophisticated, multidisciplinary environment, take ownership, and drive high-quality verification and automation processes. this position offers the opportunity to have a real impact on sophisticated, groundbreaking products, delivered by nvidia and developed by our customers, empowering the most advanced data centers in the world. this role requires close collaboration with teams across various fields (sw, hw, QA ) to elevate our product to the next level.
what you'll be doing:
lead teams of software Verification engineers, providing technical direction, career development, and performance mentorship
define and continuously refine our software testing methodology and processes
engage in a hands-on approach, actively participating in the design, coding, and debugging of verification tests and infrastructure alongside your team
lead the verification process, ensuring the functionality, stability, and performance of our doca networking sdk and the solutions on top of it
work closely with internal and external customers to understand system use cases
analyze coverage measures to identify verification gaps and provide data -driven insights into product development and release readiness

Requirements:
what we need to see:
b.sc degree or equivalent experience in Computer Science, computer engineering, or electrical engineering
10+ years of overall professional experience and 4+ years of experience managing managers or senior engineers.
proficient in Python, C, C ++ with the technical depth to guide and mentor the team
experience with regression systems and their optimizations
experience with networking protocols, mainly ethernet
experience with virtualization technologies
strong analytical, debugging, and problem-solving skills with meticulous attention to detail
experience with Embedded sw development
excellent interpersonal skills and the ability to multitask in a dynamic environment with shifting priorities
self-motivated and well-organized
ways to stand out from the crowd:
advanced understanding in ethernet protocols and rdma
experience with cloud and ai workload optimization
proficiency in continuous integration (ci) methodologies and tools such as gerrit, jenkins, and gitlab
experienced in TEST generation and coverage methods and metrics
background in Linux Kernel, security protocols

This position is open to all candidates.

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29/03/2026

DFT Engineer

חברה חסויה

Location: Tel Aviv-Yafo and Caesarea

Job Type: Full Time

We push the boundaries of technology, developing innovative DFT solutions that drive industry-leading programmability, scalability, and performance. Our team operates in a hybrid model, with three days a week in the office in Midtown Tel Aviv or Caesarea, fostering collaboration and technical excellence in a startup-like atmosphere within a stable, global corporation.

Your Impact

As an Experienced DFT Engineer, you will:

Own and drive DFT execution across the full product lifecycle, from pre-silicon design through post-silicon debug and production qualification.

Define and align DFT architecture and strategy in close collaboration with chip architects, design, and verification teams.

Oversee and contribute hands-on to the implementation of DFT features, including ATPG, scan insertion and compression, and memory BIST.

Lead silicon debug activities and root-cause analysis, driving corrective actions to improve yield, reliability, and test quality.

Establish, standardize, and evolve DFT methodologies and best practices across projects.

Requirements:
B.Sc. or M.Sc. in Electrical Engineering or a related field.

Strong hands-on experience with MBIST, and a passion for expanding expertise to scan insertion, ATPG, and boundary scan technologies.

Proven experience across the full silicon product lifecycle, from pre-silicon design to silicon bring-up and production.

Strong communication and collaboration skills.

This position is open to all candidates.

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26/03/2026

senior SOC design Verification engineer, cloud

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
in this role, you will work as part of a research and development team. you will build verification components, constrained-random testing, system testing, and drive verification closure. you will verify digital designs, collaborate closely with design and Verification engineers on projects, and perform direct verification. you will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. you will manage the full life-cycle of verification, which can range from verification planning, TEST execution, to collecting and closing coverage.the ai and infrastructure team is redefining whats possible. we empower our company customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers, our company cloud customers, and billions of our company users worldwide. we're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our company cloud, our company global networking, data center operations, systems research, and much more.
responsibilities
plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
create and enhance constrained-random verification environments using systemverilog and uvm, or formally verify designs with sva and industry leading formal tools.
identify and write all types of coverage measures for corner-cases.
debug tests with design engineers to deliver functionally correct design blocks.
close coverage measures to identify verification holes and to show progress towards tape-out.

Requirements:
minimum qualifications:
bachelor's degree in electrical engineering or equivalent practical experience.
8 years of experience with creating and using verification components and environments in standard verification methodology.
experience verifying digital logic at rtl level using systemverilog or Specman /e for fpgas or asics.
preferred qualifications:
master's degree or phd in electrical engineering, or a related field.
3 years of experience with creating and using verification components and environments in standard verification methodology.
experience with verification techniques, and the full verification life cycle.
experience with performance verification of asics and asic components.
experience with application-specific integrated circuit (asic) standard interfaces and memory system architecture.
experience in four or more system on a chip ( SOC ) cycles.

This position is open to all candidates.

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8592833

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13/04/2026

Field Application Engineer - AI Accelerators

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

Required Field Application Engineer - AI Accelerators
In this position:
You will serve as the primary technical interface between us and our customers for our AI accelerator product line and future accelerator platforms. You will support customers through the full product lifecycle - from pre-sale technical engagement and proof-of-concept development through production deployment and ongoing field support. You will work hand-in-hand with R&D to investigate and resolve complex issues, develop reference applications and demos, and act as a trusted technical advisor to both customers and internal teams.
Responsibilities
Develop a comprehensive understanding of each customers use case, system architecture, and integration requirements, serving as their primary technical point of contact for all accelerator-related topics.
Provide deep technical support across the accelerator portfolio, including the Dataflow Compiler, model compilation, and runtime integration.
Reproduce, investigate, and drive resolution of complex hardware and software issues in close collaboration with R&D, spanning PCIe integration, driver-level debugging, inference pipeline optimization, and power management.
Lead technical alignment with customers - clearly communicating issue status, setting expectations, coordinating across internal teams, and ensuring customer satisfaction.
Design and implement customer-facing demo and reference applications in C/C++, showcasing accelerator capabilities at major industry events such as CES and other trade shows.
Support pre-sale technical activities including solution scoping, feasibility assessments, and technical presentations to prospective customers.
Provide knowledge transfer and technical enablement to FAEs and partners to scale field support effectiveness.
Collaborate closely with R&D, Product, and Business teams to translate customer needs into actionable product requirements and roadmap input.

Requirements:
Bachelors degree in Electrical Engineering, Computer Engineering, or a related field
7+ years of hands-on experience as an application, software, or embedded engineer
Strong programming skills in C/C++
Deep proficiency in Linux environments, including kernel-level debugging and driver interaction
Experience with PCIe-based hardware integration and embedded system architectures
Strong debugging and problem-solving skills at the system level
Excellent interpersonal and communication skills - able to interface confidently with both engineering teams and customer stakeholders
Quick learner with the ability to span multiple technological disciplines while maintaining a strong system-level perspective
Highly organized, with the ability to manage and follow up on multiple parallel customer engagements
Fluency in English
Advantages:
Prior experience with AI inference frameworks, neural network compilation, or edge AI deployment
Hands-on experience with our products or other AI accelerator platforms
Customer-facing or FAE experience
Fluency in additional languages.

This position is open to all candidates.

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22/03/2026

Project Manager

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

Skincare technology expert Pollogen is a dynamic subsidiary of our company, a global pioneer in energy-based technology for the aesthetics and vision domains with sales in nearly 100 countries, a large and growing installed-base, and strong presence in the US, Europe, and Asia. Pollogen offers a fresh approach to innovation, specializing in professional-grade and home-use devices that provide real results. Combined with our companys six decades of market leadership, 330+ patents, 500+ clinical publications, Pollogen and our company offer the perfect balance of scientific artistry and creative excellence.
Basic Job Purpose
The Project Manager is accountable for end-to-end delivery of multidisciplinary medical device development projects, ensuring alignment between business needs, technical execution, regulatory compliance, and product lifecycle objectives.
Key Responsibilities
Full ownership of product development projects from initiation through market release and lifecycle management
Planning and execution of project scope, budget, resources, milestones, and schedules
Close collaboration with Product, Business Development, and Marketing to translate market and customer needs into technical deliverables
Leadership of multidisciplinary teams, including R&D, software, regulatory, clinical, operations, and external subcontractors
Definition and control of system-level requirements, including hardware, software, and integration aspects
Continuous monitoring of execution, risks, dependencies, and mitigation plans, with proactive decision-making
Enforcement of medical device development processes, quality systems, and regulatory standards across all disciplines
Ownership of development documentation, including DHF, DMR, and software lifecycle documentation
Accountability for verification and validation activities at system, hardware, and software levels
Leadership of transition to manufacturing, including test strategies, production readiness, and change control
Support of regulatory submissions, safety testing, root cause analysis, and implementation of corrective actions.

Requirements:
Bachelors degree in Electrical Engineering, Mechanical Engineering, or equivalent engineering discipline (mandatory)
3-5 years of proven experience managing multidisciplinary medical device development projects (mandatory)
Solid knowledge of medical device development processes, including design controls, V&V, documentation, and regulatory compliance
Strong system-level engineering mindset with ability to manage complex technical trade-offs
Practical, working understanding of software development lifecycle processes, including requirements management, architecture, implementation, testing, integration, configuration management, and change control
Experience working with software development tools and environments, including JIRA and Linux-based systems
High professional credibility, accountability, and data-driven decision-making capability
Excellent communication skills with experience working directly with senior leadership and multiple stakeholders
Advantage
Familiarity with IEC 62304 and regulated software development for medical devices
Experience with aesthetic or energy-based medical systems
Proven involvement in full product lifecycle and roadmap execution.

This position is open to all candidates.

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8586596

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22/03/2026

Senior AI System Security Architect - Networking

חברה חסויה

Location: More than one

Job Type: Full Time

We are now looking for a Senior AI System Security Architect! We are looking for an outstanding technical security architect with system architecture focus to design, validate, and guide implementation of secure architecture of its core products. The candidate is expected to: define problems and deliver highly innovative solutions that lead to significant differentiation in the industry, translate customer needs into architectural, technical & strategic direction, and help to resolve objectives & long-range goals of the security organization. Leaders in this role will help reduce risk, threats, and vulnerabilities in our Data Center products and services.

What youll be doing:

Own the security requirements for our networking systems in a variety of product lines.

Work with technical and senior leadership staff to turn business directives into functional implementations.

Collaborate between multiple business units and development groups to ensure a robust and secure product posture, from design to implementation in multiple system level products.

Provide hands-on security engineering expertise across a wide variety of platforms and services.

Provide strategic and tactical expertise in orchestrating, securing, deploying solutions; and in defining relative architectures.

This role extends across multiple groups and excellent working knowledge in the following areas of expertise is necessary for success:

Designing system security architecture at hyperscale.

Embedded systems security architecture and design.

Deep, low level understanding in Root Of Trust (ROT) technologies.

Networking security protocols and concepts.

Operating systems security and SW security concepts.

Requirements:
What we need to see:

BS / MS / Ph.D. in EE or CS. Ph.D. in CS, EE (related technical field) or equivalent preferred.

5+ years of experience in the security industry, especially in System level products including HW, FW and SW components.

Familiarity with System on Chip (SoC) level design or architecture.

Experience with system level threat modeling, risk management frameworks and risk mitigation techniques.

Experience with compute and networking systems security architecture and engineering.

Excellent communication and interpersonal skills. and a consistent track record of driving architectural solutions across organizations.

Ways to stand out from the crowd:

Proven experience in technical customer-facing roles, presenting and discussing security and system architecture requirements and solutions.

Deep understanding of data centers and cloud infrastructure security solutions.

Demonstrated success in driving security innovation across the industry.

This position is open to all candidates.

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8586498

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Senior Chip Design Engineer, Nitro Team

חברה חסויה

Location: Tel Aviv-Yafo and Haifa

Job Type: Full Time

As a member of the UC organization, youll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in our company, including support for customers who require specialized security solutions for their cloud services.

Take part in the development of cutting-edge products within a disruptive system architecture. You will have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment. We provide a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world. Annapurna Labs, as part of us, is looking for talented engineers to help us develop a semiconductor platform based on a revolutionary architecture.

Looking for exceptional senior engineers to join the top-tier team that is developing the next generation semiconductor platform, based on a revolutionary architecture. Engineers will participate in design activities, working on the next generation of our products.

You are invited to take part in developing, integrating and deploying cutting-edge technologies, starting with identification and definition of project requirements, architecture, feature development, and collaboration with the different groups.
Your design will be integrated into the nitro SoC, on millions of servers worldwide. This is an opportunity to have a large-scale impact.
As a VLSI engineer and a member of the Nitro project, you will have an impact over the device through its entire lifecycle, from the product definition stage to mass production. You will work in close collaboration with multiple groups, including Architecture, Software, Verification, Backend, and DFT.

Key job responsibilities
*Full ownership of one or more IPs within the product:
-Micro-architecture.
-RTL coding and debug.
-Synthesis and timing closure.
-Sign-off.
* Supporting the Verification and Emulation teams: Test plan, Coverage review.
* Ensuring that the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical design.

Requirements:
Basic Qualifications
- 6+ years of experience in chip design.
- Hands-on experience in micro-architecture and RTL design (Verilog / System Verilog).
- Scripting expertise in C*, Perl, Python, or TCL.
- BSc in Computer/Electrical Engineering.
- Strong communication and collaboration skills.
- Strong leadership skills and ability to own complex units.

Preferred Qualifications
- Strong knowledge of protocols (AXI, CHI, DDR, Networking, PCIe).
- Experience with Network-on-Chip (NOC) architecture.
- knowledge with coherent and non-coherent fabric design.
- Comprehensive SoC development cycle expertise (Synthesis, STA, CDC, Lint).
- Knowledge of Design Automation tools and techniques.
- Advanced degree in related technical field.

This position is open to all candidates.

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