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חברה חסויה
Location: Caesarea and Tel Aviv-Yafo
Job Type: Full Time
We push the boundaries of technology, developing innovative DFT solutions that drive industry-leading programmability, scalability, and performance. Our team operates in a hybrid model, with three days a week in the office in Midtown Tel Aviv or Caesarea, fostering collaboration and technical excellence in a startup-like atmosphere within a stable, global corporation.

Your Impact

As an Experienced DFT Engineer, you will:

Own and drive DFT execution across the full product lifecycle, from pre-silicon design through post-silicon debug and production qualification.

Define and align DFT architecture and strategy in close collaboration with chip architects, design, and verification teams.

Oversee and contribute hands-on to the implementation of DFT features, including ATPG, scan insertion and compression, and memory BIST.

Lead silicon debug activities and root-cause analysis, driving corrective actions to improve yield, reliability, and test quality.

Establish, standardize, and evolve DFT methodologies and best practices across projects.
Requirements:
B.Sc. or M.Sc. in Electrical Engineering or a related field.

Strong hands-on experience with MBIST, and a passion for expanding expertise to scan insertion, ATPG, and boundary scan technologies.

Proven experience across the full silicon product lifecycle, from pre-silicon design to silicon bring-up and production.

Strong communication and collaboration skills.
This position is open to all candidates.
 
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חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as the design for TEST (dft) engineer lead, you will play a crucial role in dft architecture and dft design, and support devices to production. you will be responsible for providing technical leadership in dft, developing flows, automation, and methodology, planning dft activities, tracking the dft quality throughout the project life-cycle, and providing sign-off dft to tapeout.the ai and infrastructure team is redefining whats possible. we empower our company customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers, our company cloud customers, and billions of our company users worldwide. we're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our company cloud, our company global networking, data center operations, systems research, and much more.
responsibilities
lead and execute dft activities in the design, implementation, and verification solutions for application-specific integrated circuits (asic).
develop dft strategy and architecture, including hierarchical dft, memory built-in self TEST (mbist), and automatic TEST pattern generation (atpg).
work with other engineering teams (e.g., design, verification, physical design) to ensure that dft requirements are met and mutual dependencies are managed.
manage a dft team planning, deliverables, and provide technical mentoring and guidance.
lead dft execution of a silicon project, planning, execution, tracking, quality, and signoff.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, or a related field, or equivalent practical experience.
8 years of experience in design for TEST from dft architecture to post silicon production support.
4 years of experience with people management.
experience with dft design and verification for multiple projects, dft specification, definition, architecture, and insertion.
experience with dft techniques and common industry tools, dft and physical design flows, and dft verification flow.
experience in leading dft activities throughout the whole asic development flow.
preferred qualifications:
master's degree in electrical engineering or a related field.
experience in post-silicon debug, TEST or product engineering.
experience in jtag and ijtag protocols and architectures.
experience in SOC cycles, silicon bring-up, and silicon debug activities.
knowledge of fault modeling techniques.
This position is open to all candidates.
 
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26/03/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? our engineering team works on groundbreaking innovations involving crafting creative solutions for dft architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. we are looking for an experienced dft engineer to join the atpg team. the position includes taking part in development of the next generation dft technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
 
working on the most advanced technologies and complex products, our dft solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
 
what youll be doing:
you will be in charge of state of the art design for TEST /atpg flows and implementation
take full atpg ownership end to end on a project, from arch & planning to pattern generation, verification and post silicon bring up and diagnosis.
inventing and maintaining automation flows that provide the short TEST time to production
Requirements:
5+ years of hands on dft/atpg experience knowledge & technical experience in dft asic design and in atpg tools
strong programming skills in scripting languages
bsc. in electrical engineering or computer engineering
quick learner, proactive and self-motivated, eager to learn and contribute, sense or ownership, commitment, and responsibility
 
ways to stand out from the crowd:
knowledge of dft including scan, bist, on-chip scan compression, fault models, atpg, and fault simulation
experience in mentor testkompress atpg tool and retargeting flow
programming languages: tcl, prl, phyton & Unix shell scripts
experience with ate and silicon bring-up
 
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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26/03/2026
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? our design-for- TEST engineering team works on groundbreaking innovations involving crafting creative solutions for dft architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. we are looking for a dft engineer to join the atpg team. the position includes taking part in development of the next generation dft technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
working on the most advanced technologies and complex products, our dft solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
Requirements:
you will be in charge of state of the art design for TEST /atpg flows and implementation
take atpg ownership on different dft aspects of a project, arch & planning, pattern generation, verification and post silicon bring up and diagnosis.
inventing and maintaining automation flows that provide the short TEST time to production
what we need to see:
b.sc. in electrical engineering or computer engineering or equivalent experience
5+ years of hands on dft/atpg knowledge & technical experience in dft asic design and in atpg tools
strong programming skills in scripting languages
quick learner, proactive and self-motivated, eager to learn and contribute, sense or ownership, commitment, and responsibility
ways to stand out from the crowd:
knowledge of dft including scan, mbist, lbist, on-chip scan compression, fault models, atpg, and fault simulation
experience in mentor testkompress atpg tool and retargeting flow
programming languages: tcl, prl, phyton & Unix shell scripts
experience with ate and silicon bring-up
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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26/03/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
we are looking for a senior chip design Verification engineer for developing the next generation dft technologies.
as a senior chip design Verification engineer in the dft team , you will verify the design and implementation of our dft technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches, nic and SOC product lines. we are working closely with a wide range of aspects - chip design, backend, verification and production testing. we are working on the most advanced technologies and complex products. our dft solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for verification of the dft design, architecture and micro-architecture using sophisticated verification methodologies.
as a member of our dft verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (testbenches, bfms, checkers, monitors), execute TEST /coverage plans, and verify the correctness of the design.
collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.
Requirements:
what we need to see:
bsc. in electrical engineering or computer engineering, or equivalent experience.
5+ years of practical verification experience.
experience in developing verification environments and random based verification for unit level and system level using verification tools (simulation tools, verilog, debug tools like simvision/debussy).
experience with Specman is a plus.
good understanding of rtl design (verilog).
strong debugging, problem solving and analytical skills.
excellent communication and social skills.
ability to work in a geographically diverse team environment.
self motivated, independent and target oriented.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Tel Aviv-Yafo
Job Type: Full Time
about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as part of our server chip design team, you will use your asic design experience to be part of a team that creates the SOC vlsi design cycle from start to finish. you will collaborate closely with design and Verification engineers in active projects, creating architecture definitions with rtl coding, and running block level simulations.in this role, you will contribute in all phases of application-specific integrated circuit (asic) designs from design specification to production. you will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver high quality SOC /rtl. you will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.the ml, systems, & cloud ai (msca) organization at our company designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our company services (search, youtube, etc.) and our company cloud. our end users, cloud customers and the billions of people who use our company services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our company clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
perform rtl development (e.g., coding and debug in verilog, systemverilog, vhdl), function/performance simulation debug, and lint/cdc/fv/upf checks.
participate in synthesis, timing/power, and fpga/silicon bring-up.
participate in TEST plan and coverage analysis of the block and SOC -level verification.
communicate and work with multi-disciplined and multi-site teams.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience architecting networking asics from specification to production.
8 years of experience in technical leadership.
experience in one of the following areas: arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
experience developing rtl for asic subsystems.
preferred qualifications:
experience working with design networking like: remote direct memory access (rdma) or packet processing and system design principles for low latency, high throughput, security, and reliability.
experience in tcp, ip, ethernet, pcie and dram including network on chip ( NOC ) principles and protocols (axi, ace, and chi).
experience architecting networking switches, end points, and hardware offloads.
understanding of packet classification, processing, queuing, scheduling, switching, routing, traffic conditioning, and telemetry.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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26/03/2026
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
we are now looking for a senior verification manager for our fc switch silicon team. as a fullchip verification manager in networking business unit, you'll lead a group of passionate engineers to design and implement the next generation state-of-the-art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
what you'll be doing:
work in a fc team, responsible to integrate and verify the switch at system level
lead and grow a team of fullchip Verification engineers
responsible to drive the fullchip verification execution, including staging plan of the projects and deliveries
provide technical guidance, mentoring, and support to engineers in the team.
work closely with multiple teams within organizations such as architecture, u-arch, full chip micro-architecture, be, and fw
dynamic verification environments planning for units infrastructures and system level
work with design/verification team which develops core units within the switch silicon.
Requirements:
what we need to see:
electrical engineering b.sc. or computer engineering b.sc. graduate with high scores or equivalent experience.
4+ years of managerial experience in a chip design or verification domain.
10+ overall years of experience in rtl design/dynamic verification.
knowledge in network protocols and/or hpc and distributed calculations - advantage.
a team player with good communication and interpersonal skills.
nvidia is widely considered to be one of the technology worlds most desirable employers. we have some of the most forward-thinking and hardworking people in the world working for us. are you creative and autonomous? do you love the challenge of crafting the highest performance & lowest power silicon possible? if so, we want to hear from you. come, join our switch silicon design team and help us build the next chip in this exciting and quickly growing field.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as a SOC physical design engineer, you will collaborate with functional design, design for testing (dft), architecture, and packaging engineers. additionally, you will solve technical problems with micro-architecture and logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.the ai and infrastructure team is redefining whats possible. we empower customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include , cloud customers, and billions of our  users worldwide. we're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for cloud, global networking, data center operations, systems research, and much more.
responsibilities
define and drive the implementation of physical design methodologies.
take ownership of one or more physical design partitions or top level.
drive to the closure of timing and power consumption of the design.
contribute to design methodology, libraries, and code review.
define the physical design related rule sets for the functional design engineers.
Requirements:
minimum qualifications:
bachelors degree in electrical engineering or equivalent practical experience.
4 years of experience with system on a chip ( SOC ) cycles.
experience with advanced design, including clock/voltage domain crossing, dft, and low power designs.
experience in high-performance, high-frequency, and low-power designs.
preferred qualifications:
masters degree in electrical engineering, or a related field.
experience coding with system verilog and scripting with transaction control language (tcl).
experience with very large scale integration (vlsi) design in SOC.
experience with multiple-cycles of SOC in asic design.
experience with layout verification and design rules.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
24/02/2026
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for a Senior Product Engineer to join a global team of a Product Engineers that own a technical success and customer satisfaction across multiple high-impact projects. This role is deeply rooted in data analytics; youll be working at the intersection of silicon, systems, and software to deliver high-value insights to customers.
Responsibilities
Performing post-silicon and system-level data analysis and providing insights on data extracted from post-silicon stages
Supporting customers with analytics platform problems solving and new features introduction
Drive integration of our companys analytics platform within customer environments, bridging silicon, test, and system-level domains.
Collaborate with R&D and data science teams to develop, validate, and improve advanced analytics algorithms.
Troubleshoot complex silicon/system issues through data-driven insights.
Partner with internal stakeholders (design, software, product) to influence roadmap and execution.
Act as a technical proffesional in customer onboarding, support, and ongoing engagement.
Requirements:
B.Sc. or M.Sc. in Electrical Engineering or a related discipline.
5+ years in IC/system product, test, or yield engineering, including deep post-silicon analytics experience.
Strong track record in data analysis and root-cause debugging at the system or silicon level.
Deep understanding of IC manufacturing, characterization, and qualification processes.
Excellent communication and interpersonal skills - especially in customer-facing situations.
Strong organizational and prioritization skills with a results-oriented mindset.
Fluency in English (written and verbal) is a must.
Preferred Qualifications
Expertise in data analytics platforms (e.g., JMP, Python, or similar).
Experience in ATE test development or digital simulation tools (e.g., HSpice, PrimeTime)- advantage.
Background in silicon lifecycle management, reliability physics, or embedded monitoring.
Familiarity with cloud platforms or ML-based analytical solutions is a plus.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
26/03/2026
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
we have been transforming computer graphics, pc gaming, and accelerated computing for more than 25 years. its a unique legacy of innovation thats fueled by great technology-and amazing people. today, were tapping into the unlimited potential of ai to define the next era of computing. an era in which our gpu acts as the brains of computers, robots, and self-driving cars that can understand the world.
the complexity of the chip has greatly increased over the years. we are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. thesystem -on-chip ( SOC ) group is seeking a top SOC Verification engineer to verify the design and implementation of the worlds leading networking socs. in this position, you will get the opportunity to craft complex networking chips and interact directly with architects, designers, and software engineers across sites. this is your chance to shape the future of computing with a world-class team! as an SOC Verification engineer, you will verify the design and implementation of our SOC technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches and nic SOC product lines. we are working closely with a wide range of aspects - chip design, dft, backend, verification and production testing. we are working on the most advanced technologies and complex products. our SOC solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for verification of the clock design elements, architecture and micro-architecture using sophisticated verification methodologies.
as a member of our SOC verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (testbenches, bfms, checkers, monitors), execute TEST /coverage plans, and verify the correctness of the design.
collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.
Requirements:
bsc. in electrical engineering or computer engineering.
2+ years of relevant experience.
good understanding of rtl design (verilog)
experience of uvm methodology.
strong debugging, problem solving and analytical skills.
excellent communication and social skills.
ability to work in a geographically diverse team environment.
self motivated, independent and target oriented.
way to stand out from the crowd:
previous experience in SOC and/or verification
experience in developing verification environments and random based verification for unit level and system level using verification tools (simulation tools, verilog, debug tools like simvision/debussy)
background with sv/uvm and Python
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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26/03/2026
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
we are now looking for a formal verification manager to join our networking team!
as a formal verification manager in networking business unit, you will lead a team of highly skilled formal engineers responsible for verifying the next generation of cutting-edge network products and gpu technologies.
this is a unique opportunity to make a real impact at the heart of ai and hpc revolution, while working in a fast-paced, innovative environment.
you will be part of a passionate and experienced team using leading formal verification tools and methodologies to ensure design correctness at the highest level. your work will influence key architectural decisions and help deliver world-class silicon solutions for data centers, high-performance computing, networking, and Storage applications.
what youll be doing:
lead and grow a team of formal Verification engineers focused on pre-silicon formal verification of complex digital designs.
define and drive formal verification strategies and methodologies to prove the correctness of designs across multiple projects.
collaborate closely with architecture, design, dv teams to identify verification needs and drive closure.
provide technical guidance, mentoring, and support to engineers in the team.
own the planning and execution of formal verification deliverables to ensure high quality and timely tapeouts.
Requirements:
bsc or msc in electrical/computer engineering, Computer Science, or mathematics.
5+ years of managerial experience in a chip design or verification domain.
8+ years of overall industry experience in formal verification, functional verification, or rtl design.
deep understanding of formal verification concepts, tools, and flows.
excellent leadership, problem-solving, and communication skills.
strong analytical and debugging abilities.
ways to stand out from the crowd:
hands-on experience with formal verification
background in developing formal testbenches, assertions, and coverage models.
managerial experience in chip design domain
a passion for recruiting, leading, mentoring engineers and building strong, collaborative teams.
This position is open to all candidates.
 
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עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
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