דרושים » חשמל ואלקטרוניקה » SOC UPF Methodology Engineer

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.
Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.

A problem isnt truly solved until its solved for all. Thats why Googlers build products that help create opportunities for everyone, whether down the street or across the globe. As a Technical Program Manager at Google, youll use your technical expertise to lead complex, multi-disciplinary projects from start to finish. Youll work with stakeholders to plan requirements, identify risks, manage project schedules, and communicate clearly with cross-functional partners across the company. You're equally comfortable explaining your team's analyses and recommendations to executives as you are discussing the technical tradeoffs in product development with engineers.
As a Technical Program Manager for Silicon engineering, you will use your technical and management experience to justify, plan, coordinate, and deliver custom silicon products. You will plan programs and manage their execution from early concepts through development to tapeout and production. You will collaborate closely with architecture, design, verification, physical implementation and manufacturing teams throughout the SoC execution life-cycle. This includes making technical decisions for the chip designs and methodology, driving project schedules, identifying risks and communicating them to all stakeholders, and managing partner teams.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Justify, plan, and coordinate the delivery of custom silicon products, ensuring they meet technical specifications and business objectives.
Drive alignment and collaboration across the internal silicon ecosystem from design and verification to supply chain and quality to ensure seamless execution and operational readiness.
Lead the development of credible schedules and milestones, proactively identifying technical or timeline risks and negotiating trade offs between what is needed and what is possible.
Guide the selection, qualification, and management of external partners serving as the primary technical and program interface.
Negotiate agreements and Statement of Works (SOWs) while managing vendor performance, quality, and costs to protect the supply chain against disruptions and capacity constraints.

Our Chip Design team is growing! Join our high-end product design team and help shape the next generation of advanced semiconductor solutions. About us our company  has been delivering tens of millions of chips annually to leading tier-1 customers in the Security, Cloud, and Computing domains. We specialize in semi-custom, high-quality solutions, going above and beyond to meet our customers needs. Our Israel Design Center is fully self-contained, covering everything from product definition and architecture to design, software, validation, and TEST - meaning real ownership and no daily late-night calls across time zones We also pride ourselves on a warm, open culture where everyone knows each other, and every engineer can clearly see the impact of their work on the final silicon. We are looking for experienced Chip Design Engineers to join our team and take a key role in RTL design, new IP development, and SOC integration As part of the design team, you will be deeply involved in architectural exploration, protocol evaluation, and hands-on design work across multiple chip blocks. Responsibilities
* RTL design and implementation of new IPs
*  SOC integration and design ownership of chip subsystems
* Exploration and evaluation of new protocols and architectural solutions
* Close collaboration with architecture, verification, validation, software, and back-end teams
* Delivering high-quality, best-in-class RTL that meets performance, power, and area goals Why Join Us?
* Work on cutting-edge, high-volume silicon products
* Real impact on end-to-end chip development
* Collaborative environment with strong technical ownership
* A stable yet agile organization with a human, people-first culture

We are looking for a Senior VLSI Verification Engineer to join the ride as we spearhead the next revolution in electronics!
Responsibilities
Develop and maintain advanced verification environments using SystemVerilog and UVM, ensuring scalability, configurability, and reusability across multiple IPs.
Design, implement, and execute comprehensive testbenches and random test suites to validate functional correctness, robustness, and corner-case behavior of complex IP within various SoC integration environments.
Drive coverage closure by defining, collecting, and analyzing code and functional coverage metrics; identify verification gaps and ensure complete validation of feature sets prior to sign-off.
Lead debug and root-cause analysis efforts in collaboration with senior verification and design engineers, leveraging carefully crafted logs, waveform analysis and assertions to isolate and resolve design or environment issues.
Collaborate closely with architecture, design, and firmware teams to ensure verification completeness, alignment with design intent, and seamless integration at the system level.
Contribute to methodology and infrastructure improvements, including reusable UVM components, automation scripts, and best practices that enhance team efficiency and verification quality.

Power the Future with us! we are a global leader in high-performance smart energy technology, and millions of products installed in over 133 countries. Our diverse product offering comprises intelligent solar inverters, battery Storage, backup systems, EV charging, and complete home energy management ecosystems. By leveraging world-class engineering capabilities and with a relentless focus on innovation, we strive to create a world where clean, green energy from the sun is the primary source of power for our homes, businesses, and just about everywhere we thrive.
We are seeking a highly experienced Senior Hardware Engineer specializing in Failure Analysis and Design Review. The ideal candidate will have a strong background in analog circuit design (preferably power electronics) and digital circuits, combined with extensive hands-on experience in troubleshooting and root cause analysis. This role involves leading failure investigations, reviewing new product designs, and mentoring team engineers to ensure best practices and high product reliability. Key Responsibilities
* Perform Failure Analysis on complex field issues in power conversion systems for the solar energy market.
* Lead Design Reviews for new products, providing insights to improve reliability and performance.
* Collaborate closely with R&D, Quality, and Manufacturing teams to resolve technical challenges.
* Mentor and guide team engineers, sharing expertise in power, analog and digital circuit design.
* Prepare detailed technical reports.
Country:
Israel
City:
Herzliya

Annapurna Labs, as part of our company, is looking for a System Integration Lead to be part of defining, shaping and integrating solutions for next generation of our cloud platforms. Our success depends on our world-class server infrastructure; were handling massive scale and rapid integration of emergent technologies.
Key job responsibilities
As System Integration Lead Engineer, you'll drive product development from initial architecture discussions through design, production, and customer deployment. You'll own critical hardware and software system integration, including architecture definition, mechanical design, thermal/power optimization, and signal integrity for high-speed interfaces (PCIe, SATA, Ethernet). Your responsibilities extend to developing robust boot flows, recovery mechanisms, remote debugging capabilities, firmware update processes, and comprehensive health monitoring systems.
You'll design and implement screening tests for production and data centers, lead fleet-level debugging, create repair procedures that maximize capacity recovery, and conduct game-days to validate failure recovery before general availability. This role requires you to define and document integration methodologies that scale across our product portfolio.
You'll lead the application of emerging technologies to large-scale deployments, directly impacting customer experience. In this fast-paced position, you'll collaborate with technology leaders across disciplines while maintaining exceptionally high standards. We seek candidates who consistently find ways to improve performance, quality, and cost-efficiency as we transform our industry.
If you're ready to push beyond today's limitations and solve complex integration challenges at scale, this role offers the opportunity to make a significant impact.

As a PNR/PD-CAD team member, you will have an impact on a wide range of activities and domains in the PD world. The team develops and supports utilities that enable an efficient work environment for the physical design teams across the world.

The role includes exploring new technologies and methodologies of first-of-its-kind designs, and the complex implementation of designs from small ones to the largest possible.
The job includes hands-on work and impact on all aspects of the design cycle, from infrastructure-related automation for design efficiency through developing internal PNR flows, which will enable improved designs - from PNR implementation through developing infra, signoff flows & verification utilities.

Responsibilities:
The job includes constant work with different teams and disciplines that interface with the PNR world, which includes Timing, power delivery, synthesis, Physical Verification, and more.
Along with the different disciplines, you will work with different teams, from vendors, PD team members and other CAD team members and discipline owners across the world to enable and improve the productivity of the PD flows.

Power the Future with us! At SolarEdge (NASDAQ: SEDG), we're a global leader in smart energy technology, with over 3,000 employees, offices in 34 countries, and millions of installations worldwide. Our innovative solutions include solar inverters, battery storage, backup systems, EV charging, and AI-based energy management. We're committed to making clean, green energy the primary power source for homes, businesses, and beyond. With the growing demand for electricity, the need for smart, clean energy sources is constantly rising. SolarEdge offers amazing opportunities to develop your skills in a multidisciplinary environment, covering everything from research and development to production and customer supply. Work with talented colleagues, tackle exciting challenges, and help create a sustainable future in an industry that's always evolving and innovating. Join us and be part of a company that values creativity, agility, and impactful work. We are looking for a Senior ASIC Verification engineer with good grasp of the entire verification process – plan, execution and sign-off, excellent analytical skills, technical skills and high motivation to join our team and take part of the success. What you will be doing:
* Create a thorough verification plan out of IP specification and implement it to completeness.
* Build UVM-compliant IP verification environment from scratch.
* Debug to find root cause of issues.
* Full-chip verification from planning stage to tape-out, including gate-level testing.
* Testing using both System Verilog and C.
* Work in a diverse environment, collaborating with power engineers, communication experts and SW developers

Country:
Israel

City:
Herzliya

Power the Future with us! At SolarEdge (NASDAQ: SEDG), we're a global leader in smart energy technology, with over 3,000 employees, offices in 34 countries, and millions of installations worldwide. Our innovative solutions include solar inverters, battery storage, backup systems, EV charging, and AI-based energy management. We're committed to making clean, green energy the primary power source for homes, businesses, and beyond. With the growing demand for electricity, the need for smart, clean energy sources is constantly rising. SolarEdge offers amazing opportunities to develop your skills in a multidisciplinary environment, covering everything from research and development to production and customer supply. Work with talented colleagues, tackle exciting challenges, and help create a sustainable future in an industry that's always evolving and innovating. Join us and be part of a company that values creativity, agility, and impactful work. We are looking for a Senior ASIC Verification engineer with good grasp of the entire verification process – plan, execution and sign-off, excellent analytical skills, technical skills and high motivation to join our team and take part of the success. What you will be doing:
* Create a thorough verification plan out of IP specification and implement it to completeness.
* Build UVM-compliant IP verification environment from scratch.
* Debug to find root cause of issues.
* Full-chip verification from planning stage to tape-out, including gate-level testing.
* Testing using both System Verilog and C.
* Work in a diverse environment, collaborating with power engineers, communication experts and SW developers.

Country:
Israel

City:
Herzliya

AWS Utility Computing (UC) provides product innovations - from foundational services such as our companys Simple Storage Service (S3) and our company Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWSs services and features apart in the industry. As a member of the UC organization, youll support the development and management of Compute, Database, Storage, Internet of Things (Iot), Platform, and Productivity Apps services in AWS. Within AWS UC, our company Dedicated Cloud (ADC) roles engage with AWS customers who require specialized security solutions for their cloud services.
Annapurna Labs develops the semiconductor platforms of the future for AWS, creating amazing products with complex architectures that push the boundaries of many fields. our company Web Services, the world's largest cloud provider, offers a highly reliable, scalable, and cost-effective infrastructure platform that powers hundreds of thousands of businesses in more than 190 countries. This is an exciting opportunity to join our company and contribute to bringing our next-generation products for the cloud market to the production stage.
Key job responsibilities
Analyze foundry Wafer Acceptance Test (WAT) data from development, corner lots, and qualification lots.
Collaborate with Test Engineering (TE) and Quality & Reliability (Q&R) teams to ensure test quality.
Recommend test plans and limits for production lots, corner lots, and pre-/post-qualification lots based on system specifications, yield, and Cpk targets.
Identify quality and reliability concerns and collaborate with TE, Q&R, and Failure Analysis (FA) teams to drive resolution.
Manage Continuous Improvement Process (CIP) activities with the foundry.
Drive test-time reduction activities based on Wafer Sort (WS) and Final Test (FT) production data.
A day in the life
As a Senior Product Engineer, you will play a crucial role in ensuring that the production of Annapurna Labs semiconductor products meets our customers' demands. Your responsibilities will include monitoring and analyzing production data, collaborating with various teams including Test Engineering and Foundry, Quality & Reliability (Q&R), Failure Analysis (FA), leading process and yield improvement initiatives
optimizing throughput, enhancing test quality, and reducing test time.
In this role, you will be fully exposed to the semiconductor production flow of all Annapurna Labs products, all semiconductor testing methodologies, and FAB process yield improvement activities.