לוח משרות דרושים ASIC / VLSI בתל אביב יפו

We are looking to hire a talented VLSI Design Engineer to join our VLSI group in Tel Aviv.
You will work alongside other talented engineers to develop our cutting-edge AI chips.
If you are motivated and skilled in VLSI and excited about AI, we want to meet you!
Responsibilities
Bring architecture requirements of our AI Chips to a power and area efficient VLSI implementation with the right performance.
Work along with verification to enable a fully functional design.
Work along with backend and DFT to converge the design into silicon.
Join the bring up of the features with SW when silicon is back in lab and the magic happens.

we are looking for forward-thinking, self-motivated engineers who thrive in fast-paced environments and "crisis times." Beyond technical excellence, successful candidates are:
Intrinsically, see the importance of every detail in "elegant solutions."
Excellent interpersonal and communication skills to work across diverse functional areas.
Schedule-driven with a desire to solve challenges that have never been solved before.
Responsibilities
Micro-Architecture & RTL: Design and implement high-quality, power-efficient RTL (Verilog/SystemVerilog) from block-level to sub-system levels.
Cross-Functional Collaboration: Partner with Architecture, Algorithm, Software, and Physical Design (PD) teams to translate product requirements into GDS-ready silicon.
Front-End Flow Management: Take ownership of "correct-by-construction" design tasks, including Synthesis, Lint, CDC/RDC (Clock/Reset Domain Crossing), and STA (Static Timing Analysis).
Verification Support: Work closely with Design Verification (DV) and Formal Verification teams to define coverage requirements, develop testbenches, and debug functional/performance issues.
Post-Silicon & Validation: Support pre-silicon emulation (FPGA, Palladium) and post-silicon validation in lab environments to ensure spec compliance.

In this role, you can lead our teams to deliver fully functional "first silicon" IP designs, from defining initial constraints through high-quality tape-out. You will have the rare and rewarding privilege of crafting upcoming products that will delight and inspire millions of customers every single day.
Responsibilities
Own the entire IP-level netlist generation and timing convergence journey, from synthesis and UPF power intent to final sign-off.
Architect and manage complex timing constraints (SDC) for both standard and custom designs, ensuring sign-off quality from day one.
Drive Full Chip and block-level timing/noise convergence, including hierarchical timing flows and power optimizations.
Collaborate closely with RTL designers to understand clock architecture, DFT teams on mode constraints, and PNR teams to achieve flawless physical convergence.
Develop and support automated block and chip-level sign-off flows, working with CAD teams to shape cutting-edge methodologies that eliminate pessimism and accelerate convergence.
Perform deep-dive signal integrity (SI) and noise analysis, drive custom IP integration, and generate block-level budgets to ensure correlation with the Full Chip.

we are looking for a Senior Design Engineer who wants to push boundaries, work hard, and help build something that has never been done before.

The Senior Design Engineer will join a team responsible for the architecture, design, and verification of a high-performance controller ASIC at the core of this new computational paradigm.

Your Day to Day
Own the design, micro-architecture, and implementation of digital logic for a high-performance ASIC
Translate system-level requirements into detailed micro-architecture and RTL designs
Develop high-quality RTL code in Verilog/SystemVerilog
Work closely with the algorithm, verification, analog, and software teams to define interfaces and ensure end-to-end functionality
Participate in design reviews, propose improvements, and ensure compliance with coding and design guidelines
Integrate and debug digital modules in simulation and lab environments
Support synthesis, timing closure, performance optimization, and power reduction activities
Collaborate with verification teams to define test plans and ensure thorough coverage
Contribute to a high-intensity startup environment where solving tough technical challenges and meeting ambitious schedules is part of the mission

At Lumissil, we are driving innovation in automotive technology, developing solutions that power the next generation of vehicles. We are looking for a Junior Engineer who is eager to learn, grow, and make an impact in a dynamic and innovative environment. This is a unique opportunity to work alongside experienced professionals, gain hands-on experience, and contribute to projects at the forefront of automotive electronics. If you are passionate about technology, curious to explore new challenges, and excited to make a real difference, Lumissil is the place to develop your skills, innovate, and grow your career. Why join us?
* Work on cutting-edge automotive projects
* Learn from a talented and supportive team
* Gain exposure to real-world automotive challenges
* Grow your career in a collaborative and inspiring environment If you’re ready to take the next step in your career and be part of something meaningful, we’d love to meet you! About The Position: As a Junior ASIC Design Engineer at Lumissil, you will take part in the full lifecycle of advanced chips that power the next generation of vehicles. This is a hands-on, growth-oriented role where you’ll work closely with experienced ASIC engineers, gain exposure to real silicon, and build a strong foundation in chip design and verification. In this role, you will:
* Be part of a professional ASIC team working on cutting-edge automotive solutions
* Support and learn from real emulation platforms used in production-grade designs
* Contribute to RTL implementation and gain practical experience in design flows
* Assist with verification and backend (BE) activities, learning industry best practices
* Participate in silicon bring-up, seeing your work come to life on real hardware This position is ideal for curious engineers who want to learn fast, take ownership, and grow into a key contributor in the world of automotive semiconductor design.

You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

As the Physical Design Group Leader, you will provide strategic and technical leadership to a team of engineers, guiding them through the entire chip design lifecycle. You will be responsible for the group's output, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

* Manage and build a world class team managing ASIC design, micro-arch, SDC constraints and integration efforts of the project.
* Translate high level goals to measurable plans and milestones. Lead RTL design, quality checks, and manage schedule for on-time delivery of key IPs.
* Work with verification and physical design teams to achieve high quality design.
* Interface with IP teams and manage schedule and delivery of IPs for successful TO.
* Guide and mentor junior engineers as required.
* Hire and retain tier one engineers and foster teamwork with cross functional collaboration.
* Build a culture of execution excellence coupled with innovation.
* Build a team of hard-working and passionate leaders as we scale.
* Maintain close interactions with NPI, Packaging, DFT, Architecture teams.
* Own power, performance and area optimization of design.

As the leader of the team, you will be responsible for delivering a state-of-the-art functional simulator for the family of routing and switching devices. This simulator is a critical product that streamlines the development process and significantly reduces time-to-market.

In this role, you will:

Lead and mentor and scale the team to 7-10 engineers, fostering a collaborative and inclusive environment
Oversee the design and delivery of a high-performance, reliable, and user-friendly behavioral model for devices
Collaborate closely with cross-functional teams including ASIC Architecture, Software, and Hardware to align goals and ensure seamless execution
Champion engineering excellence by modeling hands-on problem solving and debugging best practices
Guide team members in their professional development with tailored growth plans and regular feedback

Review micro-architecture specifications

Supervise verification team members and provide professional guidance

Implement Verification environment UVM based

Collaborate with Design engineers to resolve bugs and achieve coverage closure

Work with the firmware/Lab teams to verify chip flows

Perform debug, root-cause analysis, and post-silicon validation in the lab

The Design for Test (DFT) team is part of the design group, which focuses on logic design, RTL development, and running verification tests. Their main role is to design test structures embedded within the chip to ensure proper functionality after manufacturing. The goal is to detect potential manufacturing defects with maximum efficiency and filter out faulty units before they reach the market.

The ideal candidate is friendly, social, easygoing, with a good sense of humor, and has the ability to learn independently. They should be located in central\north Israel (Tel-Aviv\Caesarea). Strong independent work skills and job stability are important.



What You'll Do

Work in a small, agile team with an intimate atmosphere that offers direct mentoring and broad professional growth. Insert DFT logic, perform synthesis, and run Automatic Test Pattern Generation (ATPG) to ensure hardware testability. Execute Gate Level Simulations, timing checks, and DRC checks to maintain rigorous design integrity and performance standards. Run regressions and perform deep-dive debugging on simulation failures as part of the core verification process.

are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? our engineering team works on groundbreaking innovations involving crafting creative solutions for dft architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. we are looking for an experienced dft engineer to join the atpg team. the position includes taking part in development of the next generation dft technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
 
working on the most advanced technologies and complex products, our dft solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
 
what youll be doing:
you will be in charge of state of the art design for TEST /atpg flows and implementation
take full atpg ownership end to end on a project, from arch & planning to pattern generation, verification and post silicon bring up and diagnosis.
inventing and maintaining automation flows that provide the short TEST time to production