לוח משרות דרושים ASIC / VLSI בקיסריה

we are looking for a Physical Design Technical Leader.

we are looking for a ASIC Logic Design Engineering Technical Leader.
our Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

We are excited to announce that the team is undergoing rapid growth, and we are looking for a Leader, Software Engineering.
Your Impact:
You'll lead the development of core software technologies at the heart of tomorrow's leading infrastructure solutions, tackling the entire range of challenges from user-facing API-s, through high-level algorithms, all the way down to firmware.
Cultivate a high-performing team by recruiting top talent, fostering a collaborative environment, and providing mentorship and professional growth opportunities.
Provide technical guidance and support to the team, leveraging deep expertise in software development and industry trends to drive technical excellence.
Facilitate communication and collaboration between Silicon-One team and Partners.
Encourage creative problem-solving and innovation to address complex challenges and develop cutting-edge software solutions.
Craft and develop software driving the world's most complex infrastructures
Gain intimate knowledge of world-class silicon and programming models
Work with architecture and design teams to define the next generation of ASIC products being developed
Our unique team works in a startup atmosphere inside a stable and leading corporate and develops the full software stack enabling the Silicon One ASICs. Join a team of dedicated engineers with a proven track-record at delivering breakthrough products.

we are looking for a Senior Asic Design.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

We are looking for a hands-on, experienced Physical Design Engineer to join us and help define and implement next-generation AI SoC in an advanced technology node

You will play a key role in building and leading our physical design team, developing flows and methodologies, and driving the full RTL-to-GDSII implementation and signoff for one of the most advanced SoCs in the industry.

What Youll Do

Take part in shaping methodology and best practices in advanced technologies

Drive end-to-end implementation: synthesis, P&R, timing closure, and signoff

Collaborate closely with architecture and design teams on timing, floorplaning, partitioning, and power specification

Define and optimize static timing constraints, area, and power goals at block and top levels

Take part in flow development and automation to improve efficiency and quality of results

Our group is responsible for the development of next generation SoC for AI Networking Compute . The development starts from product definition through architecture, design, verification and up to implementation.

The complex SoC is a high-performance device running AI scale-out for inference workloads computer for vision and audio processing, with technologies from multi-disciplines.

We are looking for a Senior Verification Engineer to be a significant part in developing a complex and innovative SoC chip in a start-up company.

Taking full ownership of entire domain, defining the verification strategy, writing, and executing verification plan in system Verilog UVM.