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לפני 1 שעות
חברה חסויה
Location: Caesarea
Job Type: Full Time and Hybrid work
we are looking for a Senior Asic Design.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab
Requirements:
B.Sc./M.Sc. in Electrical Engineering from a top university
RTL design experience
Familiarity with UVM and functional verification methodologies
Preferred Qualifications:
Experience with MATLAB simulations and bit-exact modeling environments
Familiarity with mixed-signal systems and environments
Knowledge and hands-on experience with Clock Domain Crossing (CDC)
This position is open to all candidates.
 
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חברה חסויה
Job Type: Full Time and Hybrid work
We are looking for a hands-on, experienced Physical Design Engineer to join us and help define and implement companyys next-generation AI SOC in an advanced technology node
You will play a key role in building and leading our physical design team, developing flows and methodologies, and driving the full RTL-to-GDSII implementation and signoff for one of the most advanced SoCs in the industry.

What Youll Do
Take part in shaping methodology and best practices in advanced technologies
Drive end-to-end implementation: synthesis, P R, timing closure, and signoff
Collaborate closely with architecture and design teams on timing, floorplaning, partitioning, and power specification
Define and optimize static timing constraints, area, and power goals at block and top levels
Take part in flow development and automation to improve efficiency and quality of results
Requirements:
At least 3+ years experience with RTL2GDS flow

BSC/MSC in Electrical/Computer engineering

Deep understanding on STA principals, synthesis, and P R flow

Solid experience in physical verification and advanced process nodes

Advantages:

Top level implementation and signoff

Experience with DFT

Managerial experience
This position is open to all candidates.
 
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8473666
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חברה חסויה
Job Type: Full Time and Hybrid work
Our group is responsible for the development of the company next generation SOC for AI Networking Compute. The development starts from product definition through architecture, design, verification and up to implementation.

The complex SOC is a high-performance device running AI scale-out for inference workloads computer for vision and audio processing, with technologies from multi-disciplines.
In this position you will have end-to-end responsibility for all design flow. In this position you will be responsible for full cluster/block uarch, design, initial synth, lint, integrating and supporting PD, DFT and verification.

If you are curious, innovative, have strong technical skills with a hands-on approach, and understand the full design, system view and SW integration requirements, this position is for you!
Requirements:
7+ years of experience as a VLSI design engineer
B.Sc./M.Sc. degree in electrical/computer engineering from a leading university
Experience in defining uarch and design of complex design units.
SOC design experience.
full cluster/block uarch, design, inital synth, lint, integrating and supporting PD, DFT and verification.
Advantages
Experience in HW implementation of packet processing / Ethernet / Infiniband / RDMA Experience in high-speed interfaces DDR/PCIe - great advantage!
Leading VLSI teams/projects
Verification experience and knowledge with SV/UVM
CPU subsystem multi-core designs experience
Experience with Synthesis and STA analysis
This position is open to all candidates.
 
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8473706
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לפני 23 דקות
Location: Tel Aviv-Yafo and Caesarea
Job Type: Full Time and Hybrid work
we are looking for a ASIC Logic Design Engineering Technical Leader.
our Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab
Requirements:
B.Sc./M.Sc. in Electrical Engineering from a top university
​Minimum of 8 years of proven experience in a relevant field
RTL design experience
Familiarity with UVM and functional verification methodologies
Preferred Qualifications:
Experience with MATLAB simulations and bit-exact modeling environments
Familiarity with mixed-signal systems and environments
Knowledge and hands-on experience with Clock Domain Crossing (CDC)
This position is open to all candidates.
 
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
7 ימים
חברה חסויה
Location: Caesarea
Job Type: Full Time
We are looking for a hands-on, experienced Physical Design Engineer to join us and help define and implement next-generation AI SoC in an advanced technology node

You will play a key role in building and leading our physical design team, developing flows and methodologies, and driving the full RTL-to-GDSII implementation and signoff for one of the most advanced SoCs in the industry.

What Youll Do

Take part in shaping methodology and best practices in advanced technologies

Drive end-to-end implementation: synthesis, P&R, timing closure, and signoff

Collaborate closely with architecture and design teams on timing, floorplaning, partitioning, and power specification

Define and optimize static timing constraints, area, and power goals at block and top levels

Take part in flow development and automation to improve efficiency and quality of results
Requirements:
At least 3+ years experience with RTL2GDS flow

BSC/MSC in Electrical/Computer engineering

Deep understanding on STA principals, synthesis, and P&R flow

Solid experience in physical verification and advanced process nodes
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8469724
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
חברה חסויה
Location: Caesarea
Job Type: Full Time
looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.

Responsibilities
Lead the full verification lifecycle and methodologies. Plan, Design and Execute verification of SV/UVM Block level and Full chip environments , creating and execution test plans, tracking progress, and ensuring verification closure across diverse Mix-signals SoC simulation using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.
Requirements:
Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience.
5+ years in design verification, with strong SV/UVM proficiency (Less experienced engineers with high university grades or vast knowledge in RTL design will also be considered)
Self-motivated, ability to work, lead and drive tasks to completion.
Great interpersonal skills.
Understanding of digital ASIC design flows and SoC development methodologies. experience with SoC/full-chip verification, simulation/debug tools, and Unix/Linux environments, scripting languages (Python, etc.) and version control.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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דיווח על תוכן לא הולם או מפלה
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שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Caesarea
Job Type: Full Time
looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.



Responsibilities
Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.
Requirements:
Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience.
5+ years in design verification, with strong SV/UVM proficiency (Less experienced engineers with high university grades or vast knowledge in RTL design will also be considered)
Self-motivated, ability to work, lead and drive tasks to completion.
Great interpersonal skills.
Understanding of digital ASIC design flows and SoC development methodologies. experience with SoC/full-chip verification, simulation/debug tools, and Unix/Linux environments, scripting languages (Python, etc.) and version control.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8461546
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
לפני 1 שעות
Location: Caesarea
Job Type: Full Time
we are looking for a Electrical Post Silicon Validation HW Engineer.
In this role, you will be part of the Switch ASIC Post-Silicon Electrical Validation (EPSV) team.
* Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
* Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.
* Handle all chip validation aspects, including:
* Building validation plans.
* Performing EPSV using advanced test and measurement equipment.
* Writing tests in Python over device SDK.
* Executing tests and analyzing results.
You will gain in-depth knowledge of chip architecture, functionality, and operating modes, enabling you to debug and resolve electrical chip-related issues.
Requirements:
* Bachelors degree in Electrical or Computer Engineering.
* At least 3 years of experience in hardware or post-silicon validation.
* Hands-on experience with lab equipment performing high-speed, clock, and precise voltage measurements.
* Knowledge of high-speed interfaces and high-power DC/DC design.
Preferred Qualifications
* Experience bringing up ASICs on EVBs with Board Design, FPGA, SerDes, and Software teams.
* Proficiency in debugging issues in the lab using VNA/TDR, oscilloscopes, and phase noise analyzers.
* Experience developing testing environments, performing validation activities, and analyzing data.
* Familiarity with production testing and yield improvement.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8479737
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
7 ימים
Location: Caesarea
Job Type: Full Time
We are looking for a Senior Verification Engineer to be a significant part in developing a complex and innovative SoC chip in a start-up company.

Taking full ownership of entire domain, defining the verification strategy, writing, and executing verification plan in system Verilog UVM.
Requirements:
5+ years of experience as a Verification Engineer.
B.Sc./M.Sc. in Electrical/Computer Engineering from a leading university.
Strong knowledge of System Verilog and UVM methodology.
Experience in pre-silicon functional unit level/cluster/full chip verification.
Experience in verification of packet processing/Ethernet/RDMA/InfiniBand
Familiarity with SoC architecture, CPU subsystems, and multi-core designs.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8469709
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דיווח על תוכן לא הולם או מפלה
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סגור
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
7 ימים
חברה חסויה
Location: Caesarea
Job Type: Full Time
Our group is responsible for the development of next generation SoC for AI Networking Compute . The development starts from product definition through architecture, design, verification and up to implementation.

The complex SoC is a high-performance device running AI scale-out for inference workloads computer for vision and audio processing, with technologies from multi-disciplines.
Requirements:
7+ years of experience as a VLSI design engineer
B.Sc./M.Sc. degree in electrical/computer engineering from a leading university
Experience in defining uarch and design of complex design units.
SoC design experience.
full cluster/block uarch, design, inital synth, lint, integrating and supporting PD, DFT and verification.
Experience in HW implementation of packet processing / Ethernet / Infiniband / RDMA Experience in high-speed interfaces DDR/PCIe
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8469711
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לפני 1 שעות
Location: Caesarea
Job Type: Full Time
We are excited to announce that the team is undergoing rapid growth, and we are looking for a Leader, Software Engineering.
Your Impact:
You'll lead the development of core software technologies at the heart of tomorrow's leading infrastructure solutions, tackling the entire range of challenges from user-facing API-s, through high-level algorithms, all the way down to firmware.
Cultivate a high-performing team by recruiting top talent, fostering a collaborative environment, and providing mentorship and professional growth opportunities.
Provide technical guidance and support to the team, leveraging deep expertise in software development and industry trends to drive technical excellence.
Facilitate communication and collaboration between Silicon-One team and Partners.
Encourage creative problem-solving and innovation to address complex challenges and develop cutting-edge software solutions.
Craft and develop software driving the world's most complex infrastructures
Gain intimate knowledge of world-class silicon and programming models
Work with architecture and design teams to define the next generation of ASIC products being developed
Our unique team works in a startup atmosphere inside a stable and leading corporate and develops the full software stack enabling the Silicon One ASICs. Join a team of dedicated engineers with a proven track-record at delivering breakthrough products.
Requirements:
Bachelor's degree in Computer Science, Software Engineering, or related field
Minimum 7 years of software development experience, part of them as a manager of a development team
Proficiency in C++ and low-level programming
Demonstrated ability to design and implement complex software solutions
Proven track record of technical leadership
Preferred Qualifications:
Experience with ASIC and Network technologies
Background in large-scale distributed systems
Expertise in developing high-performance software that handles billions of packets
Advanced system design and architectural skills
Deep understanding of network state modeling and monitoring systems
This position is open to all candidates.
 
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