דרושים » הנדסה » Board Design Engineer

As a Software Development Engineer in Test on our team, you will own the quality of Nitro card embedded software and firmware. You will design, develop, and maintain test automation for embedded systems and components, covering hardware interface verification, real-time firmware behavior validation, firmware update integrity, and fleet-scale deployment confidence. You will collaborate closely with firmware development teams to troubleshoot complex system-level problems at the hardware-software boundary and ensure timely delivery of high-quality Nitro card software to AWS Cloud solutions.

Key job responsibilities
- Own the firmware test automation framework - architect, develop, and extend a Python-based validation solution that scales across multiple Nitro card generations and hardware platforms, automating test coverage across the full firmware stack from boot sequences through board management layers and card-level system integration.
- Design and implement traceable, specification-driven test cases that validate firmware functional correctness, fault tolerance, and performance across hardware components, communication interfaces, and cross-subsystem interactions.
- Optimize CI/CD pipelines by integrating pre-merge and post-merge firmware validation, defining trigger policies per hardware generation, enforcing coding-standard compliance, and reducing commit-to-validated cycle time.
- Troubleshoot complex embedded system failures by analyzing firmware logs, system traces, and hardware diagnostics, then translate field incidents into targeted regression suites that prevent recurrence.
- Collaborate with firmware and hardware teams during new-generation silicon bring-up, define test plans, drive quality gates for production release, and mentor teammates on testing best practices and system architecture.

A day in the life
You start your morning reviewing overnight CI results and triaging any firmware validation failures flagged across active Nitro card generations. Mid-morning, you pair with a firmware engineer to debug a boot-sequence regression discovered during pre-merge testing, using hardware-in-the-loop test benches and system traces. After lunch, you join a design review for a next-generation Nitro card, providing input on testability and proposing validation strategies for new subsystem interfaces. Later, you refine your test framework to improve coverage for a recently released feature, then wrap up by sharing your findings in a team knowledge-sharing session.

We're looking for exceptional engineers to join our Signal/Power-Integrity and Packaging team. A team that sits where the Silicon meets the Board, bridging the gap between what happens internally at the DIE and the overall system interconnect and the external memories and peer devices.
What sets us apart:
Small team, yet a one stop shop for IP electrical integration at the DIE level, Package design, SI/PI simulations, Layout, Board-design and advanced lab characterization.
Combining Signal-Integrity and Layout, to come up with optimized Package and PCB designs.
Holistic view of the entire interconnect, from the DIEs metals, through the Package, to the PCB traces, and all the way to the peer device.
In-depth post-silicon characterization, using advanced measurement techniques, far exceeding traditional compliance measurements.
Deep dive mentality, in both theory and the bolts and nuts that make the internal circuitry of the electrical interfaces.

The SIP (Signal-Integrity & Packaging) team is part of Annapurna-Labs Chip development team.
The team is dealing with the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
The teams work includes close work with the BackEnd team on integrating these interfaces to the Die, the package layout design of the BGAs substrate, Signal and power integrity simulations, and working with the system team to come up with optimal pin-out and optimal PCB breakout schemes.
We are looking for highly motivated Electrical Engineering graduates, or engineers with up to 3 years' experience in related fields, to join our growing team specializing in Signal Integrity and IC Package Design. The position offers a unique entry point into a diverse and multidisciplinary domain.

Key job responsibilities
Work on advanced high-speed interfaces such as PCIe, DDR and Ethernet.
End-to-end solution of high-speed interfaces; from floor-planning at the DIE level, through Package and PCB routing, addressing both robust SI/PI considerations as well as optimizing layout routing.
Signal and power integrity modeling and simulation of high-speed interconnects using advanced SI/PI simulation tools.

We are seeking a Package Layout Design Engineer to join our hardware team and contribute to the physical design of advanced IC packages for next-generation machine learning and data center ASICs.
In this role, you will execute package layout tasks from floor planning through tape out and manufacturing release, working closely with senior engineers, SI/PI, thermal, and manufacturing teams to deliver production-ready designs that meet performance, density, and reliability targets.

Key job responsibilities
- Execute package layout tasks across the design cycle: die floor planning, bump/pad assignment, RDL routing, substrate design, verification, and tape out release.
- Implement physical designs for advanced packaging architectures including 2.5D interposer, 3D-IC, fan-out wafer-level packaging, and silicon bridge technologies (e.g., CoWoS, EMIB, or similar).
- Support package floorplan development considering die placement, bump maps, power/ground distribution, signal escape routing, and decoupling capacitor placement.
- Perform RDL and substrate routing for high-density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias across multi-layer organic substrates or silicon interposers.
- Support die-level RDL routing and bump planning in coordination with ASIC physical design teams to help co-optimize the die-package interface.
- Contribute to cross-level layout co-optimization across die RDL, interposer/substrate, and PCB levels under guidance from senior engineers.
- Assist in maintaining package stack-up definitions in collaboration with SI/PI and materials engineering teams.
- Run physical verification checks (DRC, connectivity, shorts/opens) and support design closure.
- Follow and help refine package design rules and guidelines, working with OSAT partners and foundries to ensure DFM compliance.
- Collaborate with SI/PI engineers to incorporate electrical constraints into the physical layout - impedance-controlled routing, power plane optimization, and critical net shielding.

We are looking for a Senior Electrical Engineer to join our Sustaining Engineering team and play a key role in supporting the ongoing evolution of our innovative cancer treatment systems.

In this role, you will lead electrical engineering activities across design transfer and sustaining engineering, ensuring our products successfully transition from development into manufacturing while maintaining the highest standards of quality, reliability, manufacturability, and regulatory compliance.
Working closely with R&D, Manufacturing, Quality, and external suppliers, you will combine hands-on engineering with technical leadership to drive robust product solutions throughout the product lifecycle.


This is an excellent opportunity for an experienced engineer who enjoys solving complex technical challenges, mentoring others, and collaborating across multidisciplinary teams to bring life-changing medical technologies to patients worldwide.

What you will do:
Lead electrical engineering activities for Design Transfer and Sustaining Engineering projects.
Provide technical leadership and mentorship to electrical engineers within the DT & Sustaining Engineering team.
Serve as the company's subject matter expert for electrical design, supporting Design Transfer and Production activities.
Lead the transfer of electrical designs from R&D into manufacturing, ensuring manufacturability, quality, and reliability.
Partner with R&D teams to provide Design for Manufacturing (DFM) recommendations early in the development process.
Maintain and improve PCB and electrical board designs to support product robustness, manufacturability, and cost-effectiveness.
Define electrical project requirements, timelines, and budgets.
Generate and maintain complete production documentation, including PCB documentation, PCBA files, BOMs, assembly drawings, and work instructions.
Work closely with suppliers and manufacturing subcontractors throughout the product lifecycle.
Perform hands-on electrical design, testing, validation, and troubleshooting.
Develop and execute electrical test procedures and generate technical documentation and test reports.
Lead electrical design reviews and provide technical guidance to cross-functional teams.

We are looking for a Nitro System Manufacturing Integration Lead Engineer to be part of defining, shaping, and implementing manufacturing flows, test definitions, and card-to-server integration processes for Nitro-based platforms. This includes to be part of the manufacturing flow architecture, production test strategy, process stabilization, and yield optimization bridging system design intent with high-volume manufacturing execution.

Key job responsibilities
As a System Manufacturing Integration Lead Engineer, in the Nitro team, you will own the end-to-end manufacturing flows for accelerator card-to-server integration across manufacturing partner facilities driving the process from initial definition through stabilization into a scalable, high-yield mass production operation.

Key responsibilities include:
- Architect manufacturing flows - be part of the complete card-to-server integration sequence, including every process step, quality gate, and decision point from sub-assembly through system integration and tests.
- Define test strategy - be part of determining what to test, when, and at which station, covering card-level functional tests, post-integration validation, firmware provisioning, and first power-up diagnostics.
- Establish classification criteria - be part of determining pass/fail thresholds and test exit gates to maximize yield and minimize material waste.
- Drive process stabilization - work directly and on-site with manufacturing partners to implement, debug, and iterate on manufacturing flows from early builds through a locked, repeatable production process.
- Design alternative flows - develop parallel manufacturing paths to address real-world constraints such as component availability gaps, deferred card integration, and hub-based assembly models.
- Own process documentation & KPIs - maintain manufacturing flow baselines, drive process change control, and track yield, first-pass rate, cycle time, and defect Pareto.
- Lead cross-functional coordination - serve as the single point of ownership across hardware engineering, firmware, test/vetting, thermal, mechanical, and operations teams for Nitro-based accelerator servers built at scale.

We are looking for a Circuit Design Engineer to join the ride as we spearhead the next revolution in electronics!

Responsibilities
To develop IPs (Hard IP/Soft IP) in advanced process nodes (from definition, through design, post layout simulations, to full integration).
To work with experienced designers in the field and help enhance our solution for preventive maintenance.
Assist in the design and development of electronic circuits.
Conduct full simulation coverage of our circuits to ensure functionality and performance.
Collaborate with senior engineers to analyse and improve circuit designs.
Prepare and maintain documentation related to circuit designs and simulation results.
Stay updated with industry trends and advancements in circuit design and technology.
Support other engineering teams as needed.

Required Power and Signal Integrity Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
You'll set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners.
The ML, Systems, & Cloud AI (MSCA) organization designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all services (Search, YouTube, etc.) and Cloud.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities:
Design and optimize power distribution networks (PDN) across chip, package, and board levels. This includes managing power/ground planes, decoupling capacitors, and power gating strategies.
Conduct both pre-layout and post-layout power integrity simulations to analyze power and ground noise (SSN/SSO), voltage drops (IR drop), and electromagnetic interference (EMI).
Implement and verify low-power design methodologies, such as multi-voltage designs and clock gating, using power intent formats like UPF/CPF.
Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.
Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR), Spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.