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לפני 20 שעות
Location: Tel Aviv-Yafo
Job Type: Full Time
Required Senior Software Engineer, CPU, Cloud
About the job
In this role, you will work at the center of our most strategic infrastructure investments. You will join a high-impact team operating on the critical path of our hardware and software evolution, bridging the gap between compute infrastructure and the massive scale of our software stack. You will be responsible for defining the methods and technologies required to model, simulate, and analyze complex hardware systems, with a core focus on security, performance, and correctness analytics, ensuring the efficiency of our future compute platforms. As a software engineer in this group, you will act as an architect, designer, and coder taking ownership of your goal and working in close partnership with cross-functional teams to make it a reality.
You will be at the intersection of hardware design and software optimization for our next-generation high-performance compute cores. You will not just support existing infrastructure; but will be helping build the foundation of our future hardware. Because this work is on the "most critical path" for our future, you will have visibility into and influence over the core technology that powers our most intensive services. You will bridge the gap between silicon-level security research and massive-scale software implementation, working with experimental AI tools that are shaping how we verify and optimize future hardware. You will be building the foundation of our future hardware.
Responsibilities
Drive performance modeling and analysis for next-generation CPUs, while identifying architectural bottlenecks, ensure system correctness, and implement optimization strategies across hardware-software stack to maximize efficiency for compute workloads.
Design, develop, and maintain software modeling tools and simulation environments, leverage C++, Python, and AI-driven methodologies to perform studies and automate analytical workflows.
Conduct security analysis and threat modeling for hardware-software interfaces, while developing and implementing methodologies for detecting, mitigating, and analyzing side-channel and micro-architectural vulnerabilities, ensuring systems meet safety and privacy.
Explore, deploy, and scale experimental AI-driven tooling to automate verification workflows, enhance predictive modeling, and accelerate development cycles, actively contribute to expanding the team's suite of AI-assisted capabilities.
Provide technical leadership in system integration projects, guide cross-functional teams to resolve large-scale compute bottlenecks, influence architectural designs, and facilitate the successful deployment of hardware-software solutions.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience with software development in C++ programming language or 4 years of experience with an advanced degree.
Preferred qualifications:
Masters degree or PhD in Engineering, Computer Science, or a related technical field.
Experience in modern, high-performance CPU/ML architecture and micro-architecture.
Expertise in Security analytics.
Experience with Python programming language.
Demonstrated leadership in complex technical projects, including system integration and performance optimization.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Silicon Test and DFT Engineer, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.The AI and Infrastructure team is redefining whats possible. We empower customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
We're behind groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Collaborate with Architecture, Design and Verification teams to develop new product bring-up, validation, characterization, and qualification strategies and manufacturing test solutions for new High Performance Computing (HPC) products in advanced process technologies.
Verify test solutions on pre-silicon models (simulation or emulation) and develop Automated Test Equipment (ATE) test modules and binning flows.
Develop and validate test programs on Automated Test Equipment (ATE) platforms for new product integration (NPI) in preparation for high-volume manufacturing (HVM), working with ATE vendors and internal cross-functional teams.
Manage product sustainment support, including analyzing volume data, improving test time and yield, assessing test escapees and return merchandise authorizations (RMAs), localizing failures, implementing containment measures, and partnering with design, manufacturing, and quality and reliability teams to identify root causes and implement corrective actions.
Build tools, flows and methodologies to continuously improve and automate the testing life-cycle.
Requirements:
Minimum qualifications:
Bachelor's degree in Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience in test engineering.
Experience in pre-silicon validation, test content generation, automatic test equipment (ATE) program development, and post-silicon enabling from new product introduction (NPI) through high-volume manufacturing.
Experience with ASIC test methodologies (MBIST, ATPG, DFT, SerDes, and sensors).
Experience with Python, Java, C# or C/C++ and Advantest or Teradyne ATE platforms.
Preferred qualifications:
Masters in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
10 years of experience in test engineering, including product engineering.
Experience with CPU/GPU SoC architecture, design, validation and debug.
Experience in advanced testing methodologies and data analysis, including system to tester correlation, yield and test time analysis and improvement, etc.
Demonstrated expertise in developing automations for pre-silicon verification and post-silicon test-generation/test-program domains.
Inquisitive and motivated to venture into, and improve, all aspects of post-silicon testing from definition to realization.
This position is open to all candidates.
 
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לפני 21 שעות
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Staff Embedded Firmware Engineer, High Speed DSP
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Staff Embedded Firmware Engineer for High-Speed DSP, you will architect and define the low-level firmware and control loops powering the world's most advanced physical-layer communications silicon. Sitting at the critical intersection of digital signal processing (DSP), hardware-software co-design, and real-time systems, you will lead the development of adaptive algorithms, error correction (FEC), and link-telemetry frameworks. Your work will directly bridge the gap between high-performance hardware pipelines and our planetary-scale AI infrastructure, transforming complex communication systems theory into reliable, real-time silicon execution.
Responsibilities
Define the long-term firmware roadmap and hardware-software partitioning for physical-layer interfaces, determining the optimal balance between hardware-fixed logic and programmable firmwarm.
Architect advanced "in-situ" monitoring systems and firmware-driven diagnostics to track physical-layer link health, Bit Error Rate (BER) trends, and channel quality across millions of ports in real-time.
Design, model, and implement bare-metal or RTOS firmware to control high-speed transceivers, managing real-time adaptive loops, clock and data recovery (CDR), and physical-layer calibration.
Partner with TPU Systems, Networking Software, and High-Performance Computing (HPC) teams to ensure silicon firmware integrates seamlessly with global cluster management and collective communication frameworks.
Identify and de-risk hardware-software interface bottlenecks (e.g., register maps, driver latencies, and boot-up sequencing) that impact our AI infrastructure.
Requirements:
Minimum qualifications:
Bachelors degree in Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
10 years of industry experience in embedded systems/firmware, communication systems engineering, or digital signal processing (DSP) development.
Experience developing embedded software (C/C++) for high-speed physical-layer interfaces (PHY), digital transceivers, or communication subsystems.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
Expertise in Forward Error Correction (FEC) algorithms and advanced modulation schemes.
Track record defining firmware framework specifications, register maps, and Silicon Lifecycle Management telemetry for high-volume networking or AI silicon.
Background in wireless communications with deep domain knowledge of channel modeling, noise mitigation, and digital transceiver architectures.
This position is open to all candidates.
 
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06/08/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
Our Network Architecture, Modeling and Performance Insights group is seeking a skilled and driven hands-on Network Modeling Architect to conduct advanced network research and optimization while utilizing and enhancing our advanced simulation tools.

In this role, you will be a key contributor to defining the architecture and improving network performance for AI and High Performance Computing (HPC) workloads. You will be responsible for modeling advanced network topologies, configurations, logic and traffic patterns, and analyzing their effect on end-to-end performance. You will develop expertise in our simulation tools and write code daily to contribute directly to their development road map and prioritization, develop core features in the simulator, and expose the capabilities to additional users. You will take part in complex architecture decisions, define and verify the modeling assumptions, and put them to the test vs. real HW and SW performance. If you're passionate about tackling intricate challenges and contributing to comprehensive systems and working on innovative solutions, we want to hear from you.



What you'll be doing:

Analyze and model our AI and High Performance Computing offerings, deep dive into network behavior for training and inference and generate insights to directly impact the architecture of next-generation of AI systems. Conduct advanced network modeling, research and optimization using innovative simulation tools.

Write production-quality C++ and Python code daily. Hands-on modeling of advanced network topologies, configurations and traffic patterns representing real life AI workloads, and analyze their effect on the system's performance. Actively develop the simulator software solution while contributing modular and scalable code.

Actively support the HW and SW development life cycles, map existing and candidate features into the simulation domain to enable their analysis, impact assessment and optimization.

Take full independent ownership of the performance modeling roadmap for a defined set of features. Interface directly with internal clients, communicate the analysis conclusions effectively and iterate on them. Drive projects from concept to completion.

Improve the quality of the simulation as a software product, ensuring robustness and reliability.
Requirements:
What we need to see:

BSc or above in Computer Science, Electrical Engineering, or a related field

5+ years of recent hands-on coding experience with strong proficiency in C++ and Python. You must be comfortable navigating, optimizing, and contributing to a complex, large-scale codebase.

End to end system perspective - capable of bridging the gap between hardware behavior, micro-architecture, and software performance (latency/throughput).

Project ownership capability with proven ability to lead technical initiatives, prioritize features, and manage project lifecycles autonomously with minimal supervision.


Ways to stand out from the crowd:

Strong background in communication networks technology. Deep understanding of Ethernet, NVLink, and/or Infiniband technologies, data center infrastructure, and network protocols.

Familiarity with discrete event simulators (e.g., OMNeT++, SystemC, or proprietary architectural simulators).

 Advanced degree or experience focusing on computer architecture, algorithms, networking, or distributed systems.
This position is open to all candidates.
 
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05/08/2026
חברה חסויה
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
Our networking is a world-leader in building the most powerful supercomputers in the world which drive the AI and HPC industry. These rely on high performant network ASICs which connect GPUs at scale for efficient data transfer and compute. We are looking for a hardware performance modeling architect to join our team and build a network simulator used for the design, optimization and exploration of our future networking chips. The role is cross-disciplinary, collaborating with hardware and software teams across the wider company. You will solve complex problems, develop innovative solutions and be instrumental in determining the architecture of our next generation networking solutions.

What you'll be doing:

Define the Network Adapter chip architecture end to end from the market requirements through design and all product life cycles (post/pre-silicon, on deployments). Work with related industry standards & customers on deploying your tech.

Collaborate with teams across teams (physical design, logic design, system software, firmware, applications)

Develop cycle-accurate simulation components to evaluate and analyze micro-architecture and architectural options.

Explore innovative ideas to improve and optimize our chip systems performance.

Serve as a focal point within the organization and distribute the knowledge that you acquire.
Requirements:
What we need to see:

BSc/MSc in Electrical Engineering, Computer Science from a known university.

Experience in developing simulation models.

4+ years of experience in a relevant role as chip architecture or system integration

Knowledge and understanding of computing and networking systems.

Strong debug skills.

A can-do attitude and high energy with leadership and excellent interpersonal skills and possess the ability to learn complex concepts in a fast pace environment.

Utmost passion for attention to details in design and a high focus on design quality.


Ways to stand out from the crowd:

Experience and love for system architecture, CPU/GPU/Memory/Storage/Networking.

We are widely considered to be one of the tech worlds most desirable employers.

Master's degree in Electrical Engineering, Computer Science or related technical field.

5+ years of relevant practical experience.

Experience with network simulation tools (omnet, ns3, sst, gem5).
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required CPU Design for Test Engineer, Cloud
In this role, you will be part of a varied team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design-for-Test (DFT) Engineer, you will play a crucial role in DFT design, and support devices of extreme complexity to production. You will be responsible for developing flows, automation, and methodology, executing DFT activities. You will be responsible for test vectors end-to-end, from generating DFT content on complex design, debugging to coverage goals, simulating it at gate level, sign-off DFT to tapeout, and debugging Si results.The AI and Infrastructure team is redefining whats possible. We empower our customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency,
We're behind our groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Execute activities in the design, implementation, and verification of Design for Testing solutions for Application-Specific Integrated Circuit (ASICs).
Develop DFT strategy for array DFT, hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).
Perform ATPG, scan coverage debug and drive design fixes for coverage and quality improvements.
Perform DFT verification at RTL and gate level.
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT design requirements are met and mutual dependencies are managed.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
4 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools.
Experience with industry-standard Automatic Test Pattern Generation (ATPG) methods, fault modeling, and scan coverage debug.
Experience validating Memory Built-In Self-Test (MBIST) structures and Joint Test Action Group (JTAG)/ Test Access Port (TAP) controllers.
Experience running structural verification, debugging testbenches, or simulation tracking utilizing simulators.
Preferred qualifications:
Master's degree in Electrical Engineering.
Experience with the Tessent shell environment, specifically extracting Instrument Connectivity Language (ICL) networks.
Familiarity with Silicon bring-up and validation on Automatic Test Equipment (ATE) testers, including debugging hardware execution patterns.
Proficiency using Python or Tcl to manage complex Electronic Design Automation (EDA) design and sign-off flows.
This position is open to all candidates.
 
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10/08/2026
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Principal Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters.
As an Principal Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.
Key Responsibilities
Emulation Flow Execution & Implementation
Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging
Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies
Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market
System-Level Debug & Validation
Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs
Ensure rapid cycles from RTL to functional stability through systematic debug approaches
Own technical blocks and drive them to completion independently
Cross-Functional Collaboration
Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios
Ensure seamless hardware-software integration for AI infrastructure connectivity
Collaborate with Design and Verification teams to optimize emulation strategies.
Requirements:
Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field
10+ years of hands-on experience in Emulation at semiconductor companies
Deep expertise in emulation flows for large-scale chips using industry-standard emulators (Zebu, Palladium, or Veloce)
Strong background in SystemVerilog for developing, testing, and debugging complex SoC designs
Experience developing and maintaining execution flows for building, running, and debugging emulation models
"Can-do" approach with ability to own technical blocks and drive them to completion independently
Preferred Qualifications
Master's degree in Electrical Engineering, Computer Engineering, or related field
Familiarity with EDA tools for Lint, Clock Domain Crossing (CDC), simulation, and synthesis
Proficiency in scripting languages such as Python or TCL for automation and flow enhancement
Experience with standard debug environments (e.g., Verdi)
Knowledge of high-speed interface protocols (PCIe, Ethernet, CXL, UALink)
Background in hardware-software co-verification methodologies.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo
Job Type: Full Time
Cortex is expanding. We combine the high energy of a startup with the massive resources of the worlds cybersecurity leader. We aren't just processing data; we are managing hundreds of petabytes of it, waiting Cortex for you to apply your "magic" to invent the next generation of threat detection. As a Principal Software Development Engineer, you will be a cornerstone of the Cortex Detection Backend team. This role is designed for a technical powerhouse who thrives in the "sweet spot" between high-level architectural strategy and hands-on execution. You will influence our product roadmap, mentor elite engineers, and build systems that protect thousands of the world's most sensitive organizations.
Key Responsibilities
Architect & Innovate: Design and build a new set of capabilities focused on Data Analytics and Threat Detection. You will solve cloud security challenges that have never been tackled before.
Scale Without Limits: Ensure our microservices architecture remains robust and resilient under massive loads, processing millions of events per second.
Technical Leadership: Act as a technical sounding board and mentor. You will guide design discussions, conduct deep-dive research, and foster a culture of engineering excellence.
Strategic Collaboration: Work closely with Product Management, R&D leaders, and Security Researchers to define requirements and turn ambiguous problems into elegant technical solutions.
Drive Execution: Take ownership of the software development life cycle, ensuring high-velocity delivery in a fast-paced Agile environment.
Requirements:
8+ years of experience in backend software engineering.
Deep proficiency in modern backend languages.
Extensive experience with Kubernetes (K8s) and microservices architecture.
Deep understanding of both SQL and NoSQL databases, including complex data modeling and performance optimization for massive datasets.
Expertise in scaling high-availability environments while championing a culture of engineering excellence and continuous operational improvement.
Experience leading technical projects or mentoring high-performing teams.
A track record of taking full ownership of production systems and solving high-stakes engineering bottlenecks.
B.Sc. in Computer Science, Software Engineering, or equivalent practical experience (e.g., alumni of elite technological military units).
Preferred Qualifications
Experience in high-scale SaaS or cybersecurity environments.
Deep proficiency in Go or Python.
Practical experience with GCP (Google Cloud Platform).
This position is open to all candidates.
 
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05/08/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
Cortex is expanding. We combine the high energy of a startup with the massive resources of the worlds cybersecurity leader. We aren't just processing data; we are managing hundreds of petabytes of it, waiting Cortex for you to apply your "magic" to invent the next generation of threat detection. As a Principal Software Development Engineer, you will be a cornerstone of the Cortex Detection Backend team. This role is designed for a technical powerhouse who thrives in the "sweet spot" between high-level architectural strategy and hands-on execution. You will influence our product roadmap, mentor elite engineers, and build systems that protect thousands of the world's most sensitive organizations.
Key Responsibilities
Architect & Innovate: Design and build a new set of capabilities focused on Data Analytics and Threat Detection. You will solve cloud security challenges that have never been tackled before.
Scale Without Limits: Ensure our microservices architecture remains robust and resilient under massive loads, processing millions of events per second.
Technical Leadership: Act as a technical sounding board and mentor. You will guide design discussions, conduct deep-dive research, and foster a culture of engineering excellence.
Strategic Collaboration: Work closely with Product Management, R&D leaders, and Security Researchers to define requirements and turn ambiguous problems into elegant technical solutions.
Drive Execution: Take ownership of the software development life cycle, ensuring high-velocity delivery in a fast-paced Agile environment.
Requirements:
8+ years of experience in backend software engineering.
Deep proficiency in modern backend languages.
Extensive experience with Kubernetes (K8s) and microservices architecture.
Deep understanding of both SQL and NoSQL databases, including complex data modeling and performance optimization for massive datasets.
Expertise in scaling high-availability environments while championing a culture of engineering excellence and continuous operational improvement.
Experience leading technical projects or mentoring high-performing teams.
A track record of taking full ownership of production systems and solving high-stakes engineering bottlenecks.
B.Sc. in Computer Science, Software Engineering, or equivalent practical experience (e.g., alumni of elite technological military units).
Preferred Qualifications
Experience in high-scale SaaS or cybersecurity environments.
Deep proficiency in Go or Python.
Practical experience with GCP (Google Cloud Platform).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8769879
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior Silicon Physical Design Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
The AI and Infrastructure team is redefining whats possible. We empower customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.
Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience with System on a Chip (SoC) cycles.
Experience with advanced design, including clock/voltage domain crossing, DFT, and low power designs.
Experience in high-performance, high-frequency, and low-power designs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with scripting languages such as Perl, Python, or Tcl.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8782492
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
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סגור
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
04/08/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
In this role, you will be a key contributor to defining the architecture and improving network performance for AI and High Performance Computing (HPC) workloads. You will be responsible for modeling advanced network topologies, configurations, logic and traffic patterns, and analyzing their effect on end to end performance. You will develop expertise in our simulation tools and contribute directly to their development road map and prioritization, develop core features in the simulator, and expose the capabilities to additional users. You will take part in complex architecture decisions, define and verify the modeling assumptions, and put them to the test vs. real HW and SW performance.

If you're passionate about tackling intricate challenges and contributing to comprehensive systems and working on innovative solutions, we want to hear from you.

What you'll be doing:

Analyze and model our AI and High Performance Computing offerings, deep dive into network behavior for training and inference and generate insights to directly impact the architecture of next-generations of AI systems. Conduct advanced network modeling, research and optimization using innovative simulation tools.

Implement modeling of advanced network topologies, configurations and traffic patterns which represent real life AI workloads, and analyze their effect on the systems performance. Actively develop the simulator software solution while contributing modular and scalable code.

Actively support the HW and SW development life cycles, map existing and candidate features into the simulation domain to enable their analysis, impact assessment and optimization.

Take full independent ownership of the performance modeling roadmap for a defined set of features. Interface directly with internal clients, communicate the analysis conclusions effectively and iterate on them. Drive projects from concept to completion.

Improve the quality of the simulation as a software product, ensuring robustness and reliability.
Requirements:
What we need to see:

BSc or above in Computer Science, Electrical Engineering, or a related field

5+ years of hands-on coding experience with strong proficiency in C++ and Python. You must be comfortable navigating, optimizing, and contributing to a complex, large-scale codebase.

End to end system perspective - capable of bridging the gap between hardware behavior, micro-architecture, and software performance (latency/throughput).

Project ownership capability with proven ability to lead technical initiatives, prioritize features, and manage project lifecycles autonomously with minimal supervision.


Ways to stand out from the crowd:

Strong background in communication networks technology. Deep understanding of Ethernet, NVLink, and/or Infiniband technologies, data center infrastructure, and network protocols.

Familiarity with discrete event simulators (e.g., OMNeT++, SystemC, or proprietary architectural simulators).

Advanced degree or experience focusing on computer architecture, algorithms, networking, or distributed systems.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8768103
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