דרושים » ייצור ותעשייה » Electrical/Mechanical Engineering Technician - Data Center

We are hiring a Mechanical-Thermal Design Engineer to help define, shape, and integrate the next generation of our ML training and inference accelerators. In this role you will own the mechanical-thermal design of add-in / mezzanine cards, high-power GPU sleds and full ML racks. You will work shoulder-to-shoulder with HW, FW, and silicon teams to drive decisions on cooling solutions, power delivery packaging, structural integrity, and manufacturability, and will lead the mechanical-thermal engagement with our ODM, component vendors and data-center operators.

Key job responsibilities
1. Own the mechanical-thermal design of Annapurna next-generation Machine Learning sled and rack (including thermal solutions and mechanical challenges on PCB / chassis / rack level).
2. Lead and review mechanical and thermal design performed by ODM partners or contractors and component vendors.
3. Debug mechanical and thermal failures on production data center; drive root-cause to closure; take previous learnings to next products.
4. Design and execute mechanical and thermal experiments in the lab - from DOE through measurement, analysis, and corrective action.
5. Travel to ODM/manufacturer/vendor sites to monitor and review project kickoffs, device bringups and manufacturing lines.

Required Power and Signal Integrity Engineer
About the job
As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
You'll set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners.
Responsibilities
Design and optimize power distribution networks (PDN) across chip, package, and board levels. This includes managing power/ground planes, decoupling capacitors, and power gating strategies.
Conduct both pre-layout and post-layout power integrity simulations to analyze power and ground noise (SSN/SSO), voltage drops (IR drop), and electromagnetic interference (EMI).
Implement and verify low-power design methodologies, such as multi-voltage designs and clock gating, using power intent formats like UPF/CPF.
Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.
Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR), Spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.

The MLIL FLOW team is looking for a Senior Software Development Engineer to lead the design and delivery of systems software for our next-generation ML accelerator servers. We build production software to validate, initialize, monitor, and qualify these servers - from first silicon through fleet-scale deployment. We work on the physical systems that execute ML workloads: Server bring-up, hardware diagnostics, interconnect validation, power/thermal monitoring, and fleet-scale operations are our bread and butter.


Key job responsibilities
Lead the architecture and implementation of hardware validation and diagnostic software for new ML acceleration platforms.
Drive technical direction for PCIe validation, power/thermal diagnostics, and stress-testing frameworks that run across manufacturing, vetting, and production environments.
Own subsystems end-to-end: from design through implementation, testing, deployment, and operational excellence at fleet scale.
Work with Hardware, Manufacturing, EC2 teams to create coordinated software packages that enable both qualification and rapid deployment.
Debug and root-cause complex hardware/software interaction failures on first silicon and production fleet returns; drive root-cause to closure.
Build and maintain data pipelines, dashboards, and monitoring systems for fleet health and performance benchmarking.
Mentor engineers, define best practices, drive design reviews, and raise the bar for the team.
Lead multiple development initiatives in parallel, balancing schedule, risk, and technical quality across a fast-moving hardware program.

Senior Mechanical Designer We are looking for a Senior Mechanical Designer with expertise in opto-mechanical design to join our multidisciplinary development team.

Rק/וןרקג Power and Signal Integrity Engineer, PhD Graduate
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives and set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners.
Responsibilities
Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.
Simulate high speed interface electrical behavior using HSPICE or other circuit simulators.
Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR), spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.
Establish design rules and guidelines for optimal signal/power integrity during PCB and package layout, ensuring high production yield and reliability.
Document design specifications, analysis results, and validation reports to ensure compliance with standards and for future reference, while collaborating extensively with cross-functional teams, including ASIC architects, digital/analog designers, physical design/layout engineers, and system engineers.

Silicon One is seeking a CAD Engineer to join the Silicon One Physical Design team.
Meet the Team:
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
As part of our team, youll contribute to the development of our next-generation network devices-Silicon One. Our team operates in a startup-like environment within a stable and leading corporation.
Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof.
We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of our future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility.
Silicon One is a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine!
Your Impact:
You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Required Senior Silicon Physical Design Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
The AI and Infrastructure team is redefining whats possible. We empower our customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Cloud customers, and billions of users worldwide.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.
Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.

As a member of the UC organization, youll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in our company, including support for customers who require specialized security solutions for their cloud services.

Take part in the development of cutting-edge products within a disruptive system architecture. You will have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment. We provide a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world. Annapurna Labs, as part of us, is looking for talented engineers to help us develop a semiconductor platform based on a revolutionary architecture.

Looking for exceptional senior engineers to join the top-tier team that is developing the next generation semiconductor platform, based on a revolutionary architecture. Engineers will participate in design activities, working on the next generation of our products.

You are invited to take part in developing, integrating and deploying cutting-edge technologies, starting with identification and definition of project requirements, architecture, feature development, and collaboration with the different groups.
Your design will be integrated into the nitro SoC, on millions of servers worldwide. This is an opportunity to have a large-scale impact.
As a VLSI engineer and a member of the Nitro project, you will have an impact over the device through its entire lifecycle, from the product definition stage to mass production. You will work in close collaboration with multiple groups, including Architecture, Software, Verification, Backend, and DFT.

Key job responsibilities
*Full ownership of one or more IPs within the product:
-Micro-architecture.
-RTL coding and debug.
-Synthesis and timing closure.
-Sign-off.
* Supporting the Verification and Emulation teams: Test plan, Coverage review.
* Ensuring that the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical design.

we are looking for a Chip Test Engineer.
The Chip Test Engineer plays a crucial role in designing, developing, and implementing automated test for IC chips and systems for Automotive industry. The Test Engineer is responsible to define and develop tests, design test features, program test scripts, and analyze test results to ensure the quality and functionality of products. The Test Engineer collaborates with cross-functional teams to troubleshoot issues, improve test processes, and support product development efforts.
Responsibilities:
Develop and implement test strategies, plans, and procedures for ATE systems to ensure comprehensive testing of ICs.
Design and develop test features, test programs, and test scripts for automated test environment (ATE) based on product specifications and requirements.
Collaborate with design engineers, product manager, production vendors and manufacturing teams to understand product functionality, performance requirements, and testability considerations.
Conduct feasibility studies and risk assessments to identify potential challenges and develop mitigation strategies for test development and implementation.
Develop test program based on code languages C++ ,Java and Python.
Debug, troubleshoot, and resolve issues with ATE hardware, software, and test scripts to ensure reliable and accurate test results.
Analyze test data and results to identify trends, anomalies, and potential defects, and provide feedback to design and development teams for product improvement.
Develop and maintain documentation for test procedures, specifications, and configurations.
Collaborate with vendors and suppliers to evaluate and select ATE equipment, components, and software tools that meet project requirements and performance standards.
Stay abreast of industry trends, advancements in test technologies, and best practices in automated testing to drive continuous improvement in test processes and methodologies.

We are looking for a junior Embedded Software Engineer, to join us in building the next generation of networking products. Youll have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, fast-paced environment. Working for Annapurna Labs is thrilling and a constant learning experience. As an embedded SW development engineer, you will be responsible for developing features for Annapurna Labs next-generation hardware, to enable high network bandwidth and packets-per-seconds (PPS) performance, with consistently low latency. You will work to bring up a broad selection of instance types, optimized for various use cases, to suit each of our customers needs, such as varying combinations of CPU, memory, storage, and networking capabilities. As a SW development engineer, you will play a key role in shaping architecture definitions and SW system designs, and help to resolve complex customer issues. You will continuously evolve technically, while working to monitor our cloud health, maintain high quality standards, develop highly-optimized code, and provide exceptional customer satisfaction.

Key job responsibilities
We will be conducting a unique onboarding training program, where you will be studying the following with our technical experts and team leaders:
* Embedded systems basics.
* Annapurna technologies in EC2.
* Cloud compute development.
* Networking 101.