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לפני 6 שעות
Location: Tel Aviv-Yafo
Job Type: Full Time
The MLIL FLOW team is looking for a Senior Software Development Engineer to lead the design and delivery of systems software for our next-generation ML accelerator servers. We build production software to validate, initialize, monitor, and qualify these servers - from first silicon through fleet-scale deployment. We work on the physical systems that execute ML workloads: Server bring-up, hardware diagnostics, interconnect validation, power/thermal monitoring, and fleet-scale operations are our bread and butter.


Key job responsibilities
Lead the architecture and implementation of hardware validation and diagnostic software for new ML acceleration platforms.
Drive technical direction for PCIe validation, power/thermal diagnostics, and stress-testing frameworks that run across manufacturing, vetting, and production environments.
Own subsystems end-to-end: from design through implementation, testing, deployment, and operational excellence at fleet scale.
Work with Hardware, Manufacturing, EC2 teams to create coordinated software packages that enable both qualification and rapid deployment.
Debug and root-cause complex hardware/software interaction failures on first silicon and production fleet returns; drive root-cause to closure.
Build and maintain data pipelines, dashboards, and monitoring systems for fleet health and performance benchmarking.
Mentor engineers, define best practices, drive design reviews, and raise the bar for the team.
Lead multiple development initiatives in parallel, balancing schedule, risk, and technical quality across a fast-moving hardware program.
Requirements:
Basic Qualifications
- Bachelor's degree or above in Computer Science, Computer Engineering, Electrical Engineering, or related fields.
- At least 8 years of professional software development experience.

Preferred Qualifications
- Experience with hardware bring-up, ASIC/FPGA validation, or manufacturing test development.
- Proficiency in scripting languages (Python, Lua) for test automation and data analysis.
- Track record of cross-team influence and delivering results through others.
- Experience building data pipelines, ETL systems, or fleet-scale monitoring/dashboarding.
- Demonstrated project-management experience leading multiple R&D initiatives in parallel.
- Advantage: Experience with PCIe, or high-speed interconnect validation and debugging.
This position is open to all candidates.
 
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לפני 5 שעות
Location: Tel Aviv-Yafo
Job Type: Full Time
The MLIL DataPlane team is looking for a Senior Software Development Engineer to own the design and implementation of our inference data plane. We build the software that makes large models run efficiently on custom hardware - spanning model execution, memory management, data movement, and serving integration.
Our work covers the full inference path: integrating serving engines with custom hardware, developing high-performance compute kernels, enabling efficient data movement, and driving models from early validation through production. We operate at frontier scale with large distributed models.
This is a ground-up effort with rapidly evolving hardware and software. We need a senior IC who can write and optimize low-level code for custom hardware, validate model architectures end-to-end, build test and profiling infrastructure, and drive performance across the stack.

Key job responsibilities
- Develop and optimize compute kernels for a custom ML accelerator architecture, targeting production-level performance for large language model inference.
- Implement and validate LLM architectures (decoder-only, mixture-of-experts) end-to-end - from PyTorch model definition through distributed execution on custom hardware.
- Integrate custom accelerator backends into open-source ML serving frameworks (vLLM, PyTorch), including scheduler extensions, memory management, and model parallelism.
- Build and maintain test infrastructure for model correctness validation across CPU, GPU, simulator, and hardware targets.
- Profile and optimize inference workloads - identify bottlenecks, instrument critical paths, and drive latency and throughput improvements from simulation through hardware bringup.
- Own features end-to-end: from design through implementation, testing, and integration into the broader software stack.
- Contribute to CI/CD pipelines that gate model and kernel changes on correctness and performance regressions.
- Mentor engineers, drive design reviews, and raise the engineering bar across the team.
Requirements:
Basic Qualifications
- Bachelor's degree in computer science or equivalent.
- 7+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience.
- Knowledge of Machine Learning and LLM fundamentals, including transformer architecture, training/inference lifecycles, and optimization techniques.
- Knowledge of computer architecture, operating systems, and parallel computing.
- Strong proficiency in C/C++.
- Strong Linux systems knowledge.
- Experience developing compute kernels for GPUs, DSPs, or custom accelerators.
- Proven track record of owning and delivering complex software features end-to-end.

Preferred Qualifications
- Knowledge of ML frameworks including JAX, PyTorch, vLLM, SGLang, Dynamo, TorchXLA, and TensorRT.
- Experience in developing and deploying LLMs in production on GPUs, Neuron, TPU or other AI acceleration hardware, or experience with CUDA kernels or ML/low-level kernels.
- Familiarity with speculative decoding, KV cache optimization, or other LLM serving optimizations.
- Experience with distributed systems - collective communication, RDMA, or high-speed interconnect programming.
- Experience with hardware simulation environments and model validation workflows.
- Demonstrated early adopter of AI-assisted development tools - uses LLMs or code-generation agents as part of daily workflow.
This position is open to all candidates.
 
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27/04/2026
חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
We are looking for exceptional senior chip architects to join a world-class team that is reinventing how workloads run at scale.

As a Chip Architect, you will define architecture and micro-architecture across the complete product lifecycle - from initial requirements and early-stage technology exploration through design, implementation, and production deployment. You will explore and analyze architectural options for current and next-generation solutions, including new physical layer (PHY) and interconnect technologies, innovative protocols, and fundamental improvements to our hardware and software stack to make us the best place to run ML workloads and establish Annapurna Labs solutions as the industry-leading platform for Training and Inference workloads.

This role requires a top-down understanding of our complete solution stack, including system architecture, software stack, chip architecture, and microarchitecture. You will work in close collaboration with multiple groups - Software, Silicon engineering, System and Platform teams, and cross-functional teams across us. Your architectural decisions will influence the design of chips deployed on millions of servers worldwide, powering the future of AI, machine learning, and general-purpose compute. This is an opportunity to have large-scale impact on how the world builds and deploys infrastructure.
Requirements:
Basic Qualifications
- 8+ years of experience in logic design.
- 8+ years experience in chip architecture and micro-architecture.
- BSc in Computer/Electrical Engineering.
- Strong communication and collaboration skills.
- Strong leadership skills and ability to own and technically lead engineering teams.
- Strong knowledge of IO and network protocols.

Preferred Qualifications
- Strong knowledge of chip interconnect protocols (AXI, CHI).
- Experience with Network-on-Chip (NOC) architecture.
- knowledge with coherent and non-coherent fabric design.
- Comprehensive SoC development cycle expertise.
- Advanced degree in related technical field.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior Post-Silicon Validation Engineer, Networking
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
We are building a new team to lead the post-silicon validation efforts for our cutting-edge product. We're looking for highly motivated and talented engineers to join us in ensuring the quality and functionality of our next-generation networking silicon. This is a unique opportunity to be part of a foundational team and make a significant impact.
As a Silicon Validation Engineer, you'll play a pivotal role in the validation of our custom silicon solutions that power our cloud infrastructure bringing it to the highest quality level. Your expertise in post-silicon validation will be essential in identifying and resolving issues before they impact our customers, ensuring a seamless and high-performance cloud experience.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Conduct in-depth analysis into the architecture and microarchitecture of complex hardware units and features, such as packet processing pipelines and advanced networking capabilities.
Develop comprehensive post-silicon validation test plans based on a thorough understanding of the design and specifications.
Write, execute, and debug validation tests using Python or C/C++, running on Pre-Silicon (Pre-Si) emulation platforms and primarily on the silicon.
Lead the bring-up, troubleshooting, and debug efforts on silicon, identifying root causes of hardware and software issues.
Contribute to the development of test infrastructure and methodologies to improve validation efficiency and coverage.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical/Computer Engineering, Computer Science, related fields, or equivalent practical experience.
8 years of experience with functional tests for silicon validation (i.e., writing in C or C++ or Python or similar).
8 years of experience in silicon bring-up, functional validation, characterizing, and qualifying silicon.
Preferred qualifications:
Ability to learn new systems quickly and work on their own in a changing environment.
Excellent communication and collaboration skills.
Excellent problem-solving skills.
Passion for technical issues with and a strong sense of ownership.
Interest in hardware and a passion for transitioning into silicon validation.
This position is open to all candidates.
 
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חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior Board Design Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of םור direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Hardware Board Design Engineer, you will own the electrical design of complex High Performance Computing (HPC) systems. You will drive the development of next-generation AI accelerator boards, ensuring they meet signal integrity, power delivery, and thermal requirements. You will work cross-functionally with Silicon (ASIC), Signal Integrity, Power, Mechanical, and Manufacturing teams to bring products from concept to mass production.
Responsibilities
Lead the schematic capture and component selection for high-density, multi-layer Printed Circuit Boards (20+ layers) incorporating high-power ASICs (TPUs/CPUs), FPGAs, and high-speed memory (High Bandwidth Memory/DDR5).
Design and validate high-speed interfaces including Peripheral Component Interconnect Express (PCIe) Gen 6.0/7.0, 400G/800G/1.6T ethernet (PAM4). Collaborate with Signal Integrity (SI) engineers to define routing constraints and stack-up.
Design multi-phase power regulators (VRMs) capable of delivering 1000A currents with fast transient response for AI processors.
Work closely with PCB layout designers to guide placement and routing of critical signals and power planes.
Lead the lab bring-up of first-silicon/first-board. Debug complex hardware issues using oscilloscopes, Time-Domain Reflectometers (TDRs), and logic analyzers. Root-cause failures to component, assembly, or design issues.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, or equivalent practical experience.
5 years of experience in board design (schematic and layout supervision) for server, networking, or high performance computing products.
Experience in designing with serial interfaces (e.g., SerDes, PCIe, Ethernet, DDR) and signal integrity (insertion loss, crosstalk, impedance matching).
Preferred qualifications:
Experience with DC-DC power converter design and power integrity concepts.
Experience bringing up complex SoCs and debugging interaction between hardware, firmware, and software.
Proficiency with Electronic Design Automation (EDA) tools (Cadence Concept/Allegro, or similar).
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Silicon Validation Engineer, Networking
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Define, develop and execute post-silicon validation content on both pre-silicon setups and real silicon platforms in the lab.
Drive silicon from being a chip towards becoming a product.
Debug and investigate issues along cross-functional teams such as Firmware (FW), Software (SW), Design, Design Verification (DV), Architecture (ARCH) and multiple production teams.
Provide a quality functional coverage for our designs.
Test development and automation, design, implement, and maintain validation tests using scripting and programming languages (e.g., Python, C/C++).
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical/Computer Engineering, Computer Science, related fields, or equivalent practical experience.
Experience with functional tests for silicon validation using C or C++.
Experience in silicon bring-up, functional validation, characterizing, and qualifying silicon.
Preferred qualifications:
Experience in packet processing, data path, packet buffering, scheduler, networking protocols offload engine.
Experience in PCIe interface, PCIe Internal Switch, PCIe components RP/EP, and link establishment.
Experience with hardware prototyping, including hardware/software integration (i.e., pre-silicon use of emulation, software-based test, and diagnostics development).
Knowledge of L1/L2 layers, Ethernet SerDes (Serializer/Deserializer), Media Access Control+Physical Coding Sublayer (MAC+PCS).
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required RTL Design Technical Lead, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use the ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
The ML, Systems, & Cloud AI (MSCA) organization designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our services (Search, YouTube, etc.) and Cloud. Our end users are Googlers, Cloud customers and the billions of people who use our services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead the Design Activities at IPs, SubSystems(S.S) and SoC.
Plan, execute, track progress, assure quality, report status of the assigned activity.
Lead a team of designers both directly and in teams.
Define the Block/SoC level design documents such as Micro Architectural Specifications.
Own IP, S, SoC strategies for clocks, resets, and debugs. Enforce global methodologies and drive enhancements.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience in RTL Design cycle from IP to SoC and from specification to production.
8 years of experience in Technical leadership.
Experience in the following areas: RTL Design, Design Quality checks, Physical Design aspects of RTL coding, and Power.
Preferred qualifications:
Experience with synthesis techniques to improve Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
Experience with Design For Test and its impact on Design and Physical Design.
Experience with a scripting language like Python or Perl.
Knowledge in one of these areas: PCIe, UCIe, DDR, AXI, CHI, Fabrics, and ARM processors.
Knowledge of SOC architecture and assertion-based formal verification.
Knowledge of high performance and low power design techniques.
This position is open to all candidates.
 
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03/05/2026
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
we are looking for a Chip Test Engineer.
The Chip Test Engineer plays a crucial role in designing, developing, and implementing automated test for IC chips and systems for Automotive industry. The Test Engineer is responsible to define and develop tests, design test features, program test scripts, and analyze test results to ensure the quality and functionality of products. The Test Engineer collaborates with cross-functional teams to troubleshoot issues, improve test processes, and support product development efforts.
Responsibilities:
Develop and implement test strategies, plans, and procedures for ATE systems to ensure comprehensive testing of ICs.
Design and develop test features, test programs, and test scripts for automated test environment (ATE) based on product specifications and requirements.
Collaborate with design engineers, product manager, production vendors and manufacturing teams to understand product functionality, performance requirements, and testability considerations.
Conduct feasibility studies and risk assessments to identify potential challenges and develop mitigation strategies for test development and implementation.
Develop test program based on code languages C++ ,Java and Python.
Debug, troubleshoot, and resolve issues with ATE hardware, software, and test scripts to ensure reliable and accurate test results.
Analyze test data and results to identify trends, anomalies, and potential defects, and provide feedback to design and development teams for product improvement.
Develop and maintain documentation for test procedures, specifications, and configurations.
Collaborate with vendors and suppliers to evaluate and select ATE equipment, components, and software tools that meet project requirements and performance standards.
Stay abreast of industry trends, advancements in test technologies, and best practices in automated testing to drive continuous improvement in test processes and methodologies.
Requirements:
Bachelor's degree in electrical engineering, computer engineering, or a related field.
Proven 5+ years of experience in automated test development, preferably in the semiconductor or electronics industry.
Experience in programming languages such as C/C++/JAVA/Python.
knowledge of ATE hardware platforms (e.g., Advantest or Teradyne) and test methodologies (e.g., parametric testing, functional testing).
Familiarity with electronic measurement instruments (e.g., oscilloscopes, multimeters, signal generators) and test techniques for analog and digital circuits. Advantage RF test.
Excellent problem-solving skills and the ability to troubleshoot complex issues with ATE systems and test setups.
Strong communication and interpersonal skills, with the ability to work effectively in cross-functional teams.
Detail-oriented with a focus on quality, accuracy, and efficiency in test development and execution.
Ability to work independently, prioritize tasks, and manage multiple projects simultaneously in a fast-paced environment.
Preferred Qualifications
Experience in Mix-signals, high-speed interfaces testing fields.
Experience with test data analysis tools (e.g JMP, Spotfire, Yield HUB, Silicon Dash).
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior Silicon Physical Design Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
The AI and Infrastructure team is redefining whats possible. We empower our customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Cloud customers, and billions of users worldwide.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.
Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience with System on a Chip (SoC) cycles.
Experience with advanced design, including clock/voltage domain crossing, DFT, and low power designs.
Experience in high-performance, high-frequency, and low-power designs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with scripting languages such as Perl, Python, or Tcl.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior Emulation Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
Develop, execute, and debug full-chip/system on a chip (SoC) tests on emulation platforms.
Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
Define and implement various coverage measures to capture stimulus and corner-case scenarios. Work with software and post-silicon validation teams to reproduce failures on emulation.
Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out. Explore new verification and emulation methodologies and implement them.
Requirements:
Minimum qualifications:
Bachelor's degree in Computer Science, Electrical Engineering, or equivalent practical experience.
8 years of experience with full-chip/SoC verification (e.g., test definition, creation, execution, and debug).
Experience developing full-chip/SoC tests using these environments/tools: ASM, C, C++, Perspec, Threadmill, OS, or drivers.
Experience with execution and RTL/firmware/software debug on hardware emulation (e.g., ZeBu Server, Palladium, Veloce) or FPGA (e.g., EP, HAPS, Protium).
Experience with design debug tools (e.g., Verdi, Verisium).
Experience with coding and scripting in C, C++, Perl, TCL, or Python.
Preferred qualifications:
Experience in embedded software and firmware (e.g., Linux drivers, firmware validation).
Experience with associated electronic design automation (EDA) tools, automation, and flow enhancements.
Experience with coding in Verilog/SystemVerilog for design.
Understanding of SoC architecture and interfaces (e.g., CPU, DDR, PCIe, interconnect, Ethernet, etc.).
Understanding of register transfer level (RTL) to emulation/field-programmable gate array (FPGA) flows including emulation test benches (e.g., transactors/accelerated verification intellectual properties (VIPs), hybrid, in-circuit emulation).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
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חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
Your Role:

Lead the design and development of complex, high-performance, backend services within the One ecosystem, ensuring modularity and long-term maintainability.

Own the end-to-end performance of critical platform components, optimizing for massive data ingestion and low-latency processing across global environments.

Drive architectural discussions and provide high-level input on system design, steering the team toward scalable, cloud-native best practices.

Actively mentor and contribute to code reviews and technical discussions, sharing expertise and fostering a collaborative environment for continuous improvement.

Collaborate closely with Product, SRE, QA and Security teams to implement technical solutions aligned with business objectives.

Take a production-first approach to reliability; lead root cause analysis for complex distributed system issues and implement preventative measures to guarantee system reliability.
Requirements:
What Youll Need:

BSc in Computer Science or a related degree from a recognized institution, or a strong track record in server-side development with advanced technical skills.

5+ years of experience in software engineering with a demonstrated ability to work on large-scale projects and solve complex technical problems.

Proficiency in one or more modern programming languages such as Python, Kotlin, Java, Go, C#, or equivalent, with the ability to adapt to new tools and technologies.

Strong expertise with distributed systems, cloud-native architecture (e.g., Kubernetes, microservices), and APIs.

Hands-on experience with high-throughput date stores and messaging systems (e.g., Snowflake, PostgresSQL, Elasticsearch, Kafka or Redis).

Experience with cloud platforms such as AWS, Azure, or GCP, with knowledge of best practices for deploying and maintaining cloud-based services.

Strong problem-solving skills, with experience debugging and resolving production issues in complex systems.

A proactive approach to task prioritization and a history of leading technical initiatives from conception to deployment with minimal supervision.

Prior experience working in the cybersecurity industry or working with security-centric data pipelines and protocols is advantage.

Bonus: Experience or familiarity with modern frontend frameworks and an understanding of how frontend applications consume and state-manage complex backend data.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8610061
סגור
שירות זה פתוח ללקוחות VIP בלבד