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לפני 2 שעות
Location: Tel Aviv-Yafo
Job Type: Full Time
We are seeking a highly experienced engineering professional to take full technical ownership of a complex airborne platform, leading its development from early design stages through full system maturity.

This role serves as the senior technical authority for a multi-disciplinary UAV system, integrating hardware, software, aerodynamics, propulsion, communications, and navigation into a cohesive and high-performance platform.
Role Overview:
The position is responsible for end-to-end system definition, architecture, integration, and performance of a complex airborne system. It combines deep system engineering expertise with hands-on technical leadership across multiple engineering domains. You will act as a key technical focal point within the program, driving engineering decisions, system design direction, and cross-disciplinary alignment.
Key Responsibilities:
Full technical ownership of a complex UAV / airborne platform
system architecture definition and cross-domain integration (mechanical, electrical, software, propulsion, communications, navigation).
Leading system -level requirements engineering and decomposition into subsystem requirements.
Driving technical decision-making, trade-off analysis, and long-term system design strategy.
Ensuring system performance, reliability, scalability, and maintainability across the lifecycle.
Coordinating engineering activities across multiple disciplines and development teams.
Leading design reviews and ensuring technical alignment across stakeholders.
Partnering with program and engineering leadership on roadmap definition and future capabilities.
Supporting development of new platforms from concept through implementation.
Requirements:
Requirements:
B.Sc. in Engineering or related technical field (Aeronautics - advantage).
Significant experience in UAV systems or complex airborne platforms - must.
Proven experience in system -level development of multi-disciplinary platforms from early design stages.
Strong understanding of hardware/software/mechanical system interactions.
Experience with system architecture, requirements engineering, and design trade-offs.
Ability to work in complex, cross-functional engineering environments.
Strong technical leadership capabilities in matrix organizations.
M.Sc. - advantage.
Experience leading engineering teams - advantage.
This position is open to all candidates.
 
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לפני 2 שעות
Location: Tel Aviv-Yafo
Job Type: Full Time
A leading technology company in the unmanned aerial systems domain is seeking a Senior Systems Engineer to lead the end-to-end development of complex UAV platforms.

This role carries full system -level responsibility for a multi-disciplinary airborne platform, integrating engineering design, system architecture, performance optimization, and program execution.
Key Responsibilities:
Full system ownership of UAV platforms across the entire lifecycle.
Lead the design and integration of complex systems including airframe, system architecture, propulsion, energy, communications, navigation, and control.
Analyze system requirements and translate them into subsystem-level engineering requirements.
Drive system -level design processes and long-term technical decision-making.
Coordinate and synchronize multiple engineering disciplines (mechanical, electrical, software, etc.).
Lead system integration, testing, and validation activities.
Ensure delivery against quality, schedule, and cost targets.
Work in a matrix environment, influencing cross-functional teams without direct authority.
Contribute to defining technology roadmap and future platform capabilities.
Requirements:
Requirements:
Bachelors degree in Aeronautical Engineering, Mechanical Engineering, or Electrical Engineering.
Masters degree - Advantage.
At least 5 years of experience in UAV systems or complex aerospace systems development.
Proven experience working in multidisciplinary engineering environments.
Strong experience in systems engineering processes, including requirements analysis and system design.
Familiarity with aerospace standards and regulations - Advantage.
Experience in complex engineering environments involving multiple subsystems.
Strong system -level thinking with the ability to dive into technical details when required.
Experience leading technical teams or influencing cross-functional stakeholders - Advantage.
This position is open to all candidates.
 
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4 ימים
Location: Tel Aviv-Yafo
Job Type: Full Time
Satellite system Engineer We are looking for a Satellite system Engineer to lead the design and development of advanced space systems. This role covers system architecture, integration, and validation, working closely with multidisciplinary teams across the full project lifecycle.
Responsibilities Lead system engineering and architecture for satellite systems
Define and manage requirements, interfaces, and system trade-offs
Lead system reviews (SRR/PDR/CDR) and deliverables (ICD, V&V, ATP/ATR)
Manage design maturity, risks, and mitigation plans
Perform system modeling (SysML) and collaborate with cross-functional teams
Lead integration and testing, including TEST planning and analysis
Support proposals and technical marketing activities
Develop tools and analyses using MATLAB / Python / LabVIEW
Requirements:
Requirements B.Sc. in Aerospace, Electrical, Mechanical Engineering or Physics
5+ years of experience in system engineering or development of complex multidisciplinary satellite systems
Proven experience in system architecture definition, requirements management, and interface control
Experience managing system budgets (e.g., power, mass, data, propulsion)
Hands-on experience leading system reviews (SRR/PDR/CDR) and V&V / AIT activities
Experience working in matrix organizations and with cross-functional engineering teams
Strong analytical skills and experience with system modeling (e.g., SysML)
Proficiency in technical English (written and spoken) Location: Tel Aviv
This position is open to all candidates.
 
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13/04/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
Required Field Application Engineer - AI Accelerators
In this position:
You will serve as the primary technical interface between us and our customers for our AI accelerator product line and future accelerator platforms. You will support customers through the full product lifecycle - from pre-sale technical engagement and proof-of-concept development through production deployment and ongoing field support. You will work hand-in-hand with R&D to investigate and resolve complex issues, develop reference applications and demos, and act as a trusted technical advisor to both customers and internal teams.
Responsibilities
Develop a comprehensive understanding of each customers use case, system architecture, and integration requirements, serving as their primary technical point of contact for all accelerator-related topics.
Provide deep technical support across the accelerator portfolio, including the Dataflow Compiler, model compilation, and runtime integration.
Reproduce, investigate, and drive resolution of complex hardware and software issues in close collaboration with R&D, spanning PCIe integration, driver-level debugging, inference pipeline optimization, and power management.
Lead technical alignment with customers - clearly communicating issue status, setting expectations, coordinating across internal teams, and ensuring customer satisfaction.
Design and implement customer-facing demo and reference applications in C/C++, showcasing accelerator capabilities at major industry events such as CES and other trade shows.
Support pre-sale technical activities including solution scoping, feasibility assessments, and technical presentations to prospective customers.
Provide knowledge transfer and technical enablement to FAEs and partners to scale field support effectiveness.
Collaborate closely with R&D, Product, and Business teams to translate customer needs into actionable product requirements and roadmap input.
Requirements:
Bachelors degree in Electrical Engineering, Computer Engineering, or a related field
7+ years of hands-on experience as an application, software, or embedded engineer
Strong programming skills in C/C++
Deep proficiency in Linux environments, including kernel-level debugging and driver interaction
Experience with PCIe-based hardware integration and embedded system architectures
Strong debugging and problem-solving skills at the system level
Excellent interpersonal and communication skills - able to interface confidently with both engineering teams and customer stakeholders
Quick learner with the ability to span multiple technological disciplines while maintaining a strong system-level perspective
Highly organized, with the ability to manage and follow up on multiple parallel customer engagements
Fluency in English
Advantages:
Prior experience with AI inference frameworks, neural network compilation, or edge AI deployment
Hands-on experience with our products or other AI accelerator platforms
Customer-facing or FAE experience
Fluency in additional languages.
This position is open to all candidates.
 
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5 ימים
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
As a member of the UC organization, youll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in our company, including support for customers who require specialized security solutions for their cloud services.

Take part in the development of cutting-edge products within a disruptive system architecture. You will have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment. We provide a highly reliable, scalable, low-cost infrastructure platform in the cloud, which powers hundreds of thousands of businesses in 190 countries around the world. Annapurna Labs, as part of us, is looking for talented engineers to help us develop a semiconductor platform based on a revolutionary architecture.

Looking for exceptional senior engineers to join the top-tier team that is developing the next generation semiconductor platform, based on a revolutionary architecture. Engineers will participate in design activities, working on the next generation of our products.

You are invited to take part in developing, integrating and deploying cutting-edge technologies, starting with identification and definition of project requirements, architecture, feature development, and collaboration with the different groups.
Your design will be integrated into the nitro SoC, on millions of servers worldwide. This is an opportunity to have a large-scale impact.
As a VLSI engineer and a member of the Nitro project, you will have an impact over the device through its entire lifecycle, from the product definition stage to mass production. You will work in close collaboration with multiple groups, including Architecture, Software, Verification, Backend, and DFT.

Key job responsibilities
*Full ownership of one or more IPs within the product:
-Micro-architecture.
-RTL coding and debug.
-Synthesis and timing closure.
-Sign-off.
* Supporting the Verification and Emulation teams: Test plan, Coverage review.
* Ensuring that the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical design.
Requirements:
Basic Qualifications
- 6+ years of experience in chip design.
- Hands-on experience in micro-architecture and RTL design (Verilog / System Verilog).
- Scripting expertise in C*, Perl, Python, or TCL.
- BSc in Computer/Electrical Engineering.
- Strong communication and collaboration skills.
- Strong leadership skills and ability to own complex units.

Preferred Qualifications
- Strong knowledge of protocols (AXI, CHI, DDR, Networking, PCIe).
- Experience with Network-on-Chip (NOC) architecture.
- knowledge with coherent and non-coherent fabric design.
- Comprehensive SoC development cycle expertise (Synthesis, STA, CDC, Lint).
- Knowledge of Design Automation tools and techniques.
- Advanced degree in related technical field.
This position is open to all candidates.
 
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5 ימים
חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
We are looking for exceptional senior chip architects to join a world-class team that is reinventing how workloads run at scale.

As a Chip Architect, you will define architecture and micro-architecture across the complete product lifecycle - from initial requirements and early-stage technology exploration through design, implementation, and production deployment. You will explore and analyze architectural options for current and next-generation solutions, including new physical layer (PHY) and interconnect technologies, innovative protocols, and fundamental improvements to our hardware and software stack to make us the best place to run ML workloads and establish Annapurna Labs solutions as the industry-leading platform for Training and Inference workloads.

This role requires a top-down understanding of our complete solution stack, including system architecture, software stack, chip architecture, and microarchitecture. You will work in close collaboration with multiple groups - Software, Silicon engineering, System and Platform teams, and cross-functional teams across us. Your architectural decisions will influence the design of chips deployed on millions of servers worldwide, powering the future of AI, machine learning, and general-purpose compute. This is an opportunity to have large-scale impact on how the world builds and deploys infrastructure.
Requirements:
Basic Qualifications
- 8+ years of experience in logic design.
- 8+ years experience in chip architecture and micro-architecture.
- BSc in Computer/Electrical Engineering.
- Strong communication and collaboration skills.
- Strong leadership skills and ability to own and technically lead engineering teams.
- Strong knowledge of IO and network protocols.

Preferred Qualifications
- Strong knowledge of chip interconnect protocols (AXI, CHI).
- Experience with Network-on-Chip (NOC) architecture.
- knowledge with coherent and non-coherent fabric design.
- Comprehensive SoC development cycle expertise.
- Advanced degree in related technical field.
This position is open to all candidates.
 
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26/03/2026
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
description
we are a global leader in control systems for quantum computing, a field on the verge of exponential growth.
our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands.
at the core of our company lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers.
our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field.
join our cutting-edge hardware development team as micro-architect and play a key role in defining and implementing the micro-architecture of advanced digital logic components.
what you'll do:
define and develop micro-architecture for complex logic blocks - from concept through high-quality rtl implementation
collaborate closely with architecture, verification, design and software design teams
write clear and detailed design specifications and drive architectural trade-off analysis
optimize for performance and area
contribute to innovation, methodology improvements, and technical leadership within the team.
Requirements:
b.sc. or higher in electrical engineering, computer engineering, or related field- must
8+ years of experience in rtl design using verilog/systemverilog- must
proven experience in designing micro-architecture for complex systems
strong system -level understanding and problem-solving skills.
This position is open to all candidates.
 
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26/03/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
we are seeking a highly motivated system Software manager to lead a team driving the development of next-generation communication software and products, building on our industry-leading nvlink and nvswitch technologies. this role combines technical leadership with hands-on development activities, driving innovation at the core ofdata center ecosystem.
what you will be doing:
lead, mentor, and grow your engineering team while overseeing project planning, execution, and ensuring the quality and performance of all deliverables.
own major features and drive the teams roadmap that aligns with ambitious goals and dynamic customer requirements.
grow the local team while collaborating with a wide range of cross-business unit teams both on-site and locally.
continuously evaluate and identify opportunities to improve processes, infrastructure, and practices to ensure efficient, transparent, and high-quality team execution.
this is a technical leadership role, with active involvement in feature design and implementation.
Requirements:
what we need to see:
bs or ms degree in computer engineering, Computer Science, or related field or equivalent experience.
8+ years of overall technical experience in system software and networking product development.
3+ years of experience managing and leading engineering teams.
experience balancing multiple projects with competing priorities.
solid understanding of computer system architecture, operating system and Kernel internals.
strong understanding of networking fundamentals and high-performance interconnection (e.g., infiniband, ethernet)
experience with Linux development, familiarity with os virtualization technologies.
background in multi-core / multi-process / multi-threaded programming environment.
ability and flexibility to work and communicate effectively in a multi-national, multi-time-zone corporate environment.
This position is open to all candidates.
 
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חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as the design for TEST (dft) engineer lead, you will play a crucial role in dft architecture and dft design, and support devices to production. you will be responsible for providing technical leadership in dft, developing flows, automation, and methodology, planning dft activities, tracking the dft quality throughout the project life-cycle, and providing sign-off dft to tapeout.the ai and infrastructure team is redefining whats possible. we empower our company customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers, our company cloud customers, and billions of our company users worldwide. we're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our company cloud, our company global networking, data center operations, systems research, and much more.
responsibilities
lead and execute dft activities in the design, implementation, and verification solutions for application-specific integrated circuits (asic).
develop dft strategy and architecture, including hierarchical dft, memory built-in self TEST (mbist), and automatic TEST pattern generation (atpg).
work with other engineering teams (e.g., design, verification, physical design) to ensure that dft requirements are met and mutual dependencies are managed.
manage a dft team planning, deliverables, and provide technical mentoring and guidance.
lead dft execution of a silicon project, planning, execution, tracking, quality, and signoff.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, or a related field, or equivalent practical experience.
8 years of experience in design for TEST from dft architecture to post silicon production support.
4 years of experience with people management.
experience with dft design and verification for multiple projects, dft specification, definition, architecture, and insertion.
experience with dft techniques and common industry tools, dft and physical design flows, and dft verification flow.
experience in leading dft activities throughout the whole asic development flow.
preferred qualifications:
master's degree in electrical engineering or a related field.
experience in post-silicon debug, TEST or product engineering.
experience in jtag and ijtag protocols and architectures.
experience in SOC cycles, silicon bring-up, and silicon debug activities.
knowledge of fault modeling techniques.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo
Job Type: Full Time
about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as part of our server chip design team, you will use your asic design experience to be part of a team that creates the SOC vlsi design cycle from start to finish. you will collaborate closely with design and Verification engineers in active projects, creating architecture definitions with rtl coding, and running block level simulations.in this role, you will contribute in all phases of application-specific integrated circuit (asic) designs from design specification to production. you will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver high quality SOC /rtl. you will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.the ml, systems, & cloud ai (msca) organization at our company designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our company services (search, youtube, etc.) and our company cloud. our end users, cloud customers and the billions of people who use our company services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our company clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
perform rtl development (e.g., coding and debug in verilog, systemverilog, vhdl), function/performance simulation debug, and lint/cdc/fv/upf checks.
participate in synthesis, timing/power, and fpga/silicon bring-up.
participate in TEST plan and coverage analysis of the block and SOC -level verification.
communicate and work with multi-disciplined and multi-site teams.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience architecting networking asics from specification to production.
8 years of experience in technical leadership.
experience in one of the following areas: arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
experience developing rtl for asic subsystems.
preferred qualifications:
experience working with design networking like: remote direct memory access (rdma) or packet processing and system design principles for low latency, high throughput, security, and reliability.
experience in tcp, ip, ethernet, pcie and dram including network on chip ( NOC ) principles and protocols (axi, ace, and chi).
experience architecting networking switches, end points, and hardware offloads.
understanding of packet classification, processing, queuing, scheduling, switching, routing, traffic conditioning, and telemetry.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo
Job Type: Full Time
about the job
in this role, youll work to shape the future of ai/ml hardware acceleration. you will have an opportunity to drive cutting-edge tpu (tensor processing unit) technology that powers google's most demanding ai/ml applications. youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of google's tpu. you'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on tpu architecture and its integration within ai/ml-driven systems.
as a design technology co-optimization (dtco) engineer, you will bridge the gap between process technology and product architecture to define the next generation of datacenter-class silicon. you will be responsible for extracting maximum process entitlement by evaluating advanced logic nodes and emerging transistor architectures.in this role, you will conduct place and route experiments and sensitivity analyses to influence standard cell library architecture, metal stack definitions, and design rules. you will collaborate with foundry, ip, and architecture teams to identify power, performance, and area (ppa) bottlenecks and drive system technology co-optimization (stco) initiatives.your work will involve performing high-fidelity physical implementation sweeps, analyzing the impact of scaling boosters, and developing automated methodologies to quantify ppa gains. by navigating the trade-offs between process complexity and design performance, you will ensure googles hardware achieves efficiency and power density.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
execute high-fidelity place and route experiments to evaluate the ppa impact of advanced process features, library architectures, and design rule variations on datacenter-class ip.
drive design technology co-optimization by collaborating with foundries and internal technology teams to define optimal metal stacks, track he
דרישות:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, or a related field, or equivalent practical experience.
2 years of experience in physical design (rtl-to-gds) or technology development, focusing on advanced nodes (e.g., 7nm, 5nm, or below).
experience with industry-standard place and route (p&r) tools and static timing analysis (sta) tools.
experience in cmos device physics, finfet/nanosheet architectures, and the impact of layout parasitics on ppa.
experience in scripting and automation using tcl and Python (or PERL ) to manage design sweeps and data extraction.
preferred qualifications:
master's degree or phd in electrical engineering, computer engineering or Computer Science, with an emphasis on computer architecture.
experience in design technology co-optimization (dtco), including standard cell library characterization, metal stack optimization, and evaluation of scaling boosters (e.g., backside power delivery).
experience working with major foundry technology files (pdks) and interpreting design rule manuals (drm) to guide physical im המשרה מיועדת לנשים ולגברים כאחד.
 
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עדכון קורות החיים לפני שליחה
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