דרושים » חשמל ואלקטרוניקה » OCS Lead Design Engineer

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
As a Design Team Manager within the Server Chip Design team, you will oversee the IP and SoC VLSI design cycle from architecture to production. In this role, you will own and manage IP, subsystems and SoC development, leading a group of designers and design tech leads.
You will be responsible for mentoring and developing team members and tech leads while driving improvements in leadership, technical execution, and design flows.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead design activities at IPs, subsystems, and SoC.
Plan, execute, track progress, assure quality, and report status of the assigned activity.
Work closely with internal customers and support multiple activities and deliverables.
Assure and manage deliverables quality at all RTL design categories including reviews, static checks, design for physical design, power, etc.

*Employment as a contractor through a third-party agency* MSD Animal Health Technology Labs specializes in the development of animal health management solutions. We are a multidisciplinary product company, a diverse team of ~450 closely collaborating scientists, AI experts, software, hardware, and mechanical engineers… working alongside veterinarians and other animal experts. Our passion? Shaping the future of animal health and well-being (for much better!). Our products and platforms identify trends and predict the likelihood of health outcomes for HUNDREDS of MILLIONS of animals each year, from pets, to poultry, farm animals, and even fish. We provide actionable insights for veterinarians, farmers, and producers, changing the way people care for animals in 150 markets. So, if you’re looking to work in a company that combines pioneering science and technology, dedicated colleagues, and animals, you’ll find it all here – come join us!
As System Integration engineer you will define setups, test plans and own test execution and debug, while working inside a demanding and diverse eco system. Position requires the ability to develop test plans, lead technical investigations of complex system issues as well as creative problem solving and hands on approach.
Responsibilities: · Detailed definitions of test plans and test cases. · Detailed definitions of testing setups. · Hands-on debug of complex system.

DRS RADA is a global pioneer of RADAR systems for active military protection, counter-drone applications, critical infrastructure protection, and border surveillance. We are looking for a talented Technical Manager to join our team. Core Mission: Ensure rigorous quality assurance throughout the development lifecycle of hardware-based radar systems, driving toward zero defects in design, testing, and pre-production phases. Lead quality planning, risk mitigation, and compliance for multiple radar development projects running in parallel. Key Responsibilities:
* Develop and execute quality assurance plans tailored to hardware development (radar systems), focusing on materials, components, assembly, integration, and validation.
* Define hardware-specific KPIs/KGIs (e.g., First Pass Yield, Test Coverage, Defect Density in prototyping, Non-Conformance Rates)
* Act as quality authority in hardware-focused design reviews:
* SRR (System Requirements Review) – Ensure requirements are testable and meet standards.
* PDR (Preliminary Design Review) – Assess design maturity, component selection, and tolerancing.
* CDR (Critical Design Review) – Verify design readiness for prototyping, focusing on manufacturability, reliability, and safety.
* TRR (Test Readiness Review) – Validate test setups, instrumentation, and acceptance criteria.
* PRR (Production Readiness Review) – Ensure design is transition-ready with robust quality controls.
* Conduct hardware-focused FMEA on RF modules, power systems, structural elements, thermal management, and integration interfaces.
* Implement preventive/corrective actions to address identified failure modes early in development.
* Oversee design verification testing (DVT) and reliability testing (e.g., HALT/HASS, thermal cycling, vibration, EMI/EMC).
* Approve test plans, procedures, and reports for hardware performance and compliance.
* Chair Change Control Board (CCB) meetings for hardware changes (BOM revisions, component substitutions, drawing updates).
* Maintain traceability of requirements, designs, tests, and revisions.
* Ensure adherence to AS9100 and MIL STD as 810,882,461
* Support safety certification processes (functional safety for hardware subsystems) according to MIL- STD-882
* Lead cross-functional Root Cause Analysis (e.g., 8D, 5Why) for hardware non-conformances.
* Drive systematic corrections into design and development processes to prevent recurrence.
* Collaborate with suppliers on critical components (e.g., PCBA, antennas, enclosures) to ensure design intent is met and quality is built in.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
As a Design & Power Methodology Team Manager within the Server Chip Design team, you will be responsible of managing and leading design and power methodologies from IP to SoC, pre and post silicon. You will be responsible for mentoring and developing team members and tech leads while driving improvements in leadership, technical execution, and design flows.
You will work closely with CAD vendors and internal teams to develop lead design and power methodology and execution.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead flow and methodology development and assimilation across multiple groups. Work closely with CAD tool providers as well as internal CAD teams.
Plan, execute, track progress, assure quality, and report status.
Work closely with internal customers and support multiple activities and deliverables.
Drive design methodologies such as design construction, CDC, RDC, SDC. Drive power at: IP and SoC RTL/Gate Level Optimization, estimation, correlation.

We specialize in the development of animal health management solutions. We are a multidisciplinary product company, a diverse team of ~450 closely collaborating scientists, AI experts, software, hardware, and mechanical engineers working alongside veterinarians and other animal experts. Our passion? Shaping the future of animal health and well-being (for much better!). Our products and platforms identify trends and predict the likelihood of health outcomes for HUNDREDS of MILLIONS of animals each year, from pets, to poultry, farm animals, and even fish. We provide actionable insights for veterinarians, farmers, and producers, changing the way people care for animals in 150 markets. So, if youre looking to work in a company that combines pioneering science and technology, dedicated colleagues, and animals, youll find it all here come join us! About the role: The role is in the global Engineering department part of the operation sector located in Nethanya site. The position represents Change analyst & Documentation Configuration control focal point, with NPI capabilities. We are looking for a highly skilled and motivated Change analyst & Documentation Configuration control engineer to maintain the PLC of all products families under the engineering responsibility, using & expert with the PLM & ERP systems. The position perfect for someone who thrives on structure, accuracy with extensive communication interfaces, departments and functions in the company such as engineering, regulatory, logistic, procurement, quality, production (inhouse & CMOs), import & export, Legal, information systems, sub-contractors, RnD, project managers. Key Responsibilities
* Maintaining PLM & ERP system
* Establish and enforce best practices for BOM & revisions management
* Support systems validation, upgrades, improvements and users. Creation & control of part numbers, BOMs, revisions, statuses, production processes, work procedures & instruction, flowcharts, workflows.
* ECR, ECO (CCB), MCO, EOL management till full implementation
* Autonomy ability leading those process that required NPI capabilities, and hands-on activity
* Perform as CMOs, vendors & company stakeholders focal point for engineering data transfer, updates and documentation control.
* Own and maintain the end-to-end configuration control process across all product lines.
* Ensure product data accuracy, consistency, and compliance across the entire lifecycle.
* Part of approval chain
* Integrated process support with operation logistic, procurement, production, quality.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing Application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.You will also be responsible for performance analysis for a networking stack.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead an ASIC subsystem.
Understand how ASIC subsystem interacts with software and other ASIC subsystems to implement data center networks.
Define hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

Annapurna Labs, as part of our company, is looking for a System Integration Lead to be part of defining, shaping and integrating solutions for next generation of our cloud platforms. Our success depends on our world-class server infrastructure; were handling massive scale and rapid integration of emergent technologies.
Key job responsibilities
As System Integration Lead Engineer, you'll drive product development from initial architecture discussions through design, production, and customer deployment. You'll own critical hardware and software system integration, including architecture definition, mechanical design, thermal/power optimization, and signal integrity for high-speed interfaces (PCIe, SATA, Ethernet). Your responsibilities extend to developing robust boot flows, recovery mechanisms, remote debugging capabilities, firmware update processes, and comprehensive health monitoring systems.
You'll design and implement screening tests for production and data centers, lead fleet-level debugging, create repair procedures that maximize capacity recovery, and conduct game-days to validate failure recovery before general availability. This role requires you to define and document integration methodologies that scale across our product portfolio.
You'll lead the application of emerging technologies to large-scale deployments, directly impacting customer experience. In this fast-paced position, you'll collaborate with technology leaders across disciplines while maintaining exceptionally high standards. We seek candidates who consistently find ways to improve performance, quality, and cost-efficiency as we transform our industry.
If you're ready to push beyond today's limitations and solve complex integration challenges at scale, this role offers the opportunity to make a significant impact.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

This role is for an analog layout IP lead who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of silicon development from definition to high quality production.

Senior Layout Leads are responsible for delivering Analog Mixed-Signal IP in an SOC flow. They collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs.
As a member of the AMS layout team you will be responsible to deliver Physical Design Verification clean layout, this includes the following:
Crafting complex layout for mixed signal, and analog circuits in deep SubMicron CMOS technologies.
Reviewing and analyzing floor-plans and complex circuits with circuit designers.
Running complete set of design verification tools available on AMS blocks.
Working with the circuit design team to plan/schedule work and negotiate any necessary layout trade-offs as needed.
Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout.
Exceeding engineering specifications and expectations by working closely with the circuit design team.
Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.

Responsibilities:
Overall responsibility for precision tracking technical project management at R&D including planning and monitoring of all R&D activities, planning and monitoring of project R&D budget (material and hours), lead of technical activities with the customer including design reviews, acceptance testing and system assimilation.
Overall responsibility of the system level architecture of complex systems
Overall responsibility for System, Software and Hardware level specifications and requirements.
Overall responsibility and active participation in the Integration and Proof of Design phases.
Overall responsibility for electrical connectivity design between LRUs.