דרושים » תוכנה » Senior VLSI Backend Engineer

Requirements:
BSc or MSc in Electrical Engineering or Computer Engineering
8+ years of VLSI experience.
Experience with multi clock domain, multi power domain designs (UPF).
Methodologic approach.
Strong Motivated to learn quickly, hard-working, and is results-oriented.
Great interpersonal relations skills.
Preferred
Networking design experience - Major Advantage
Backend experience: STA tools, formal equivalence tools, frontend/backend handoff methodologies.
SoC design/Integration experience.
Proven Methodologies and Environmental Building Experience.
Strong proficiency in scripting language, such as, Perl, Tcl, Python, Make, and automation methods/algorithms.

Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering.

7+ years of actual design experience in chip design.

Strong RTL proficiency in SystemVerilog for reading/debugging designs and implementing CDC/RDC-safe structures.

Experience with constraints and timing intent (SDC) and their interaction with CDC/RDC.

Hands-on expertise with industry CDC/RDC tools (e.g., SpyGlass, Questa CDC, Real Intent) and lint/formal where relevant.

Proficiency in at least one scripting languages like Python, bash, Perl, TCL.

Great teammate.

Way to stand out from the crowd:

Passion for quality. Experience with delivery to physical design and other customers.

Requirements:
What we need to see:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering.
2+ years proven experience in chip design.
Solid hands-on RTL design skills in System-Verilog.
Proficiency in at least one scripting languages like python, bash, tcl.
Great teammate.

Way to stand out from the crowd:
Passion for quality. Experience with delivery to physical design, emulation, firmware and other customers.

Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent experience.

2+ years of experience.

Proven experience in RTL2GDS flows and methodologies. (advantage)

Knowledge in physical design flows and methodologies (PNR, STA, physical verification). (advantage)

Deep understanding of all aspects of Physical construction and Integration.

Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

Great teammate.

Requirements:
What we need to see:
B.Sc./M.Sc. in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
5+ years of experience in VLSI CAD tool development, with a strong focus on integrating AI/ML techniques into EDA workflows.
Proficiency in Python and at least one AI/ML framework (such as TensorFlow, PyTorch, or scikit-learn).
Hands-on experience with VLSI physical design and familiarity with industry-standard EDA tools (e.g., Synopsys, Cadence).
Knowledge of data preprocessing, feature engineering, and model deployment as applied to VLSI design challenges.
Experience developing and maintaining automation scripts (Python, Perl, Tcl, Make).
Strong analytical skills in evaluating the impact of AI solutions on design quality, performance, and productivity.
Excellent communication skills and the ability to work cross-functionally in a fast-paced environment.
Self-motivation, attention to detail, and a track record of delivering robust solutions to production.

Ways to stand out from the crowd:
Demonstrated experience deploying AI/ML models in production VLSI CAD environments.
Contributions to open-source AI/EDA projects or publications in relevant conferences/journals.
Deep understanding of VLSI design challenges-such as timing closure, power optimization, or yield enhancement-and how AI can address them.
Experience with cloud-based or distributed compute environments for large-scale AI training and inference.
Strong ownership, curiosity, and a passion for continuous learning and innovation.

Requirements:
A degree in Electrical Engineering or a related field.

2+ years of experience in VLSI physical build and integration flows automation.

Strong knowledge in VLSI build/layout and basic programming/scripting skills.

Familiarity with EDA layout tools such as Cadence Virtuoso, Synopsis Fusion Compiler, or Siemens Calibre.

Advantageous to have experience with UNIX, VBA, TCL, or PERL scripting.

Experience or knowledge in power integrity is a plus.

Requirements:
BSc or MSc in Electrical Engineering or Computer Engineering.
4-7 years of experience in FPGA prototyping or emulation of ASIC/SoC designs
Strong understanding of digital design and RTL (Verilog/SystemVerilog/VHDL).
Hands-on experience with at least one emulation/prototyping platform (Palladium, Protium, Veloce, ZeBu, or FPGA-based)
Good knowledge of synthesis, timing closure, and design partitioning for FPGA/emulation.
Familiarity with verification methodologies and environments (UVM/SystemVerilog/C).
Experience with scripting (TCL, Python, Perl, or Shell) for automation.
Strong problem-solving and debugging skills.
Ability to work in a fast-paced, collaborative environment.
Excellent communication and teamwork skills.
Preferred:
Exposure to software bring-up, driver validation, or firmware testing on emulation.
Knowledge of bus protocols (Ethernet, DDR, etc.).
Experience with debug tools (waveform viewers, logic analyzers, or emulation debug frameworks).
Background in SoC architecture and hardware/software co-design.

Requirements:
Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience.
8+ years of experience in Verification or HW simulation.
Knowledge in SoC architecture, network protocols - advantage.
Innovation Mindset: A proactive approach to adopting new methodologies and coding tools to solve complex challenges.

Requirements:
B.Sc. in Electrical Engineering or a related field.
6+ years of experience in ASIC/SoC Verification.
Experience leading verification planning and execution independently.
Preferred:
Familiarity with RDMA, Ethernet, DDR or RISC-V.