Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
As a Design & Power Methodology Team Manager within the Server Chip Design team, you will be responsible of managing and leading design and power methodologies from IP to SoC, pre and post silicon. You will be responsible for mentoring and developing team members and tech leads while driving improvements in leadership, technical execution, and design flows.
You will work closely with CAD vendors and internal teams to develop lead design and power methodology and execution.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead flow and methodology development and assimilation across multiple groups. Work closely with CAD tool providers as well as internal CAD teams.
Plan, execute, track progress, assure quality, and report status.
Work closely with internal customers and support multiple activities and deliverables.
Drive design methodologies such as design construction, CDC, RDC, SDC. Drive power at: IP and SoC RTL/Gate Level Optimization, estimation, correlation.

We are seeking a CAD Engineer to join the Physical Design team.

You'll be joining our Physical Design team within us, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

We are looking for a Physical Design Engineer
Roles and Responsibilities:
Build, maintain, and optimize CAD tools infrastructure supporting both commercial and in-house layout and verification tools (Cadence Virtuoso, Synopsys ICC, Mentor Calibre, etc.).
Develop and automate IC layout flows, including placement, routing, floorplanning, PCells, and tapeout preparation.
Apply advanced software engineering and CAD methodologies to address technical challenges, evaluate architectural and hardware constraints, and deliver scalable automation solutions.
Collaborate with layout, circuit, and verification teams to capture requirements and deploy efficient automation workflows.
Design and implement testing frameworks, regression suites, code review practices and CI/CD pipelines to validate CAD flows, ensure correctness, and improve reliability.
Define, document, and enforce best practices, standards, and procedures; provide technical guidance, training, and support to engineering teams.

We are looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:
Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).
Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.
Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks.
Taking part in flows development and deployment.

Are you ready to be part of a team that's pushing the boundaries of technology and innovation? At NVIDIA, we're leading the way in transforming computer graphics, PC gaming, and accelerated computing. We're now beginning the next era of modern AI computing. As a Backend Chip Integration Engineer, you will play a crucial role in building the future of our powerful technologies. This is an outstanding opportunity for those who are passionate about VLSI physical design and automation flows.

What you'll be doing:

Define chip interface and silicon interposer interface, focusing on their physical location and netlist.

Develop automation flows for chip integration and power grid implementation.

Perform power integrity analysis of the interposer power grid to ensure flawless performance.

Collaborate with cross-functional teams to successfully implement world-class solutions.

Contribute to the continuous improvement of our integration processes with your innovative ideas and expertise.

Join a dynamic and innovative team driving the development of state-of-the-art EDA/CAD tools and scalable design automation infrastructure to empower advanced integrated circuit (IC) design. You will design, develop, and maintain next-generation design robust software tools and workflows across all domains in integrated circuit design, while ensuring compatibility with legacy software solutions.
Roles and responsibilities
Build, maintain, and optimize CAD tools supporting both commercial and in-house layout and verification tools (Cadence Virtuoso, Synopsys ICC, Mentor Calibre, etc.).
Develop and automate design flows spanning frontend RTL-to-GDSII, digital backend implementation, and physical/verification signoff, ensuring scalability and tapeout readiness.
Collaborate with layout, circuit, and verification teams to capture requirements and deploy efficient automation workflows.
Apply advanced software engineering and CAD methodologies to address technical challenges, evaluate architectural and hardware constraints, and deliver scalable automation solutions.
Design and implement testing frameworks, regression suites, code review practices, and CI/CD pipelines to validate CAD flows, ensure correctness, and improve reliability.
Define, document, and enforce best practices, standards, and procedures; provide technical guidance, training, and support to engineering teams.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
As a Design Team Manager within the Server Chip Design team, you will oversee the IP and SoC VLSI design cycle from architecture to production. In this role, you will own and manage IP, subsystems and SoC development, leading a group of designers and design tech leads.
You will be responsible for mentoring and developing team members and tech leads while driving improvements in leadership, technical execution, and design flows.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead design activities at IPs, subsystems, and SoC.
Plan, execute, track progress, assure quality, and report status of the assigned activity.
Work closely with internal customers and support multiple activities and deliverables.
Assure and manage deliverables quality at all RTL design categories including reviews, static checks, design for physical design, power, etc.

We are looking for a creative and experienced Senior Firmware Engineer to join our PCIe Firmware team-someone passionate about using artificial intelligence to engineer the foundational hardware of the AI revolution.

As an integral part of our team, you'll architect and implement the core of our next-generation devices. This senior role places you at the center of innovation, where you will have a direct impact on our business and technology by solving sophisticated technical challenges. Its a unique opportunity to shape our technology and empower customers to build the supercomputers and AI fabrics of tomorrow.

What You'll Be Doing:
Lead the architectural design, development, and optimization of cutting-edge PCIe firmware, using AI-driven modeling and insights to deliver exceptional performance.

Serve as a trusted technical expert by investigating, debugging, and resolving challenging PCIe firmware issues for our most important customers.

Collaborate closely with our Chip Design, Verification, Software, and Architecture engineers to find root causes and develop robust, long-term solutions.

Champion the integration of AI-assisted diagnostics and generative AI tools across the entire development lifecycle to boost team productivity and innovation.

Translate customer needs and field data into actionable feedback that directly shapes the future of our products.

We are driving innovation in automotive technology, developing solutions that power the next generation of vehicles. We are looking for a Junior Engineer who is eager to learn, grow, and make an impact in a dynamic and innovative environment. This is a unique opportunity to work alongside experienced professionals, gain hands-on experience, and contribute to projects at the forefront of automotive electronics. If you are passionate about technology, curious to explore new challenges, and excited to make a real difference, we are the place to develop your skills, innovate, and grow your career.
Why join us?
* Work on cutting-edge automotive projects.
* Learn from a talented and supportive team.
* Gain exposure to real-world automotive challenges.
* Grow your career in a collaborative and inspiring environment.
If youre ready to take the next step in your career and be part of something meaningful, wed love to meet you!
About The Position:
As a Junior ASIC Design Engineer, you will take part in the full lifecycle of advanced chips that power the next generation of vehicles. This is a hands-on, growth-oriented role where youll work closely with experienced ASIC engineers, gain exposure to real silicon, and build a strong foundation in chip design and verification. In this role, you will:
* Be part of a professional ASIC team working on cutting-edge automotive solutions.
* Support and learn from real emulation platforms used in production-grade designs.
* Contribute to RTL implementation and gain practical experience in design flows.
* Assist with verification and backend (BE) activities, learning industry best practices.
* Participate in silicon bring-up, seeing your work come to life on real hardware This position is ideal for curious engineers who want to learn fast, take ownership, and grow into a key contributor in the world of automotive semiconductor design.

We are looking for a Senior networking test engineer with strong system‑level debugging skills to join our End‑to‑End Verification team. You will work on cutting‑edge Ethernet‑based AI clusters, owning complex issues across hardware, system software and AI workloads. We are widely considered to be one of the technology worlds most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!

What youll be doing:

Design and review test and product requirements across the Ethernet / NIC / DPU / Switch portfolio, focusing on large‑scale AI cluster behavior.

Build and maintain realistic customer‑like testbeds, including heterogeneous hardware, OS / driver combinations and complex network fabrics.

Own end‑to‑end cluster troubleshooting: reproduce customer scenarios, triage across the stack and drive issues to root cause and fix.

Read and understand relevant source code to identify defects, validate fixes and improve logging and instrumentation.

Collaborate closely with development teams to debug NCCL, RoCE/RDMA and related networking components using logs, code inspection and targeted experiments.

Define tests and guide the automation team to implement robust suites that produce actionable logs, metrics and traces.

Run Regression, Performance, Functional and Scale testing, analyze results and provide clear, data‑driven reports to stakeholders.

Profile and benchmark deep learning training and inference workloads, correlating model‑level metrics with system and network telemetry to uncover bottlenecks.