דרושים » הנדסה » Senior ASIC Verification Engineer

We are looking for Emulation & Prototyping Engineer
Roles and responsibilities:
Build and maintain FPGA/emulation platforms for large-scale SoC/ASIC designs.
Map RTL designs to FPGA/emulation platforms.
Develop test environments and infrastructure for HW/SW co-verification.
Support hardware bring-up and software validation on emulation platforms.
Collaborate with verification engineers to run regressions and accelerate debug cycles.
Optimize partitioning, synthesis, and runtime performance on emulation systems.
Work cross-functionally with RTL design, verification, and firmware/software teams.


Join our Networking Silicon team as a Senior Full-Chip ASIC Engineer. In this role, you will be responsible for the development and verification of our next-generation NICs at the system level. You will contribute to the architecture of high-speed communication devices by building advanced simulation platforms and driving full-chip verification execution for the networking solutions powering the worlds most advanced data centers.

What youll be doing:
Full-Chip Verification & Execution: Own complex system-level features by defining verification plans and driving the end-to-end execution.
Software Simulation Development: Architect and code robust software simulation platforms that serve as the foundation for Firmware development and uArchitectural research
AI-Enhanced Engineering: Accelerate development by leveraging cutting-edge AI coding tools and frameworks.
Global Technical Collaboration: Partner with Architecture, FW, and SW engineering teams across the globe to deliver industry-leading networking solutions

We are looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:
Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).
Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.
Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks.
Taking part in flows development and deployment.

We are looking for talented and ambitious individuals to join our Yoqneam IC team.
Roles and responsibilities
The candidate will join our BE team, focusing on Full-Chip floor-planning, timing closure and integration, collaborating closely with frontend design, architecture, physical design, and analog teams. Additionally, the candidate will provide support to design teams across various methodologies and contribute to project execution efforts.
What will the candidate be doing
Lead Full Chip Layout activities & methodologies for a brand new SoC, from definition to Tape Out.
Floor Planning Top to Bottom & Bottom up - FC, Sub System & Block level.
Involved in chip architecture, in close collaboration with the packaging, design & architecture teams. Exploring different floorplan structures to achieve both best area & ease of convergence.
Drive sign-off timing convergence for high performance designs at Full-chip and building block level.
Involved in definition of overall STA methodology, STA infrastructure and sign-off convergence flows, working closely with block owners throughout the project for sign-off timing convergence.
Work closely with EDA (Electronic Design Automation) vendors on latest tool feature development and qualification.

We are looking for talented and ambitious individuals to join our Yoqneam IC team.
Roles and responsibilities:
Join a team of VLSI frontend design engineers in Chain-Reactions projects.
Define, plan and implement our next chip in Chain-Reactions on-going product line and in a new product line of cryptography algorithms acceleration SoCs.
Work closely with multiple teams within organizations such as Architecture, BE, Circuit, Analog and FW
Responsible for scaling up the frontend design environment methodologies.

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Design-for-Test Engineering team works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for a DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.

Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!

What youll be doing:

You will be in charge of state of the art Design for Test/ATPG flows and implementation.

Take ATPG ownership on different DFT aspects of a project, Arch & planning, pattern generation, verification and post Silicon bring up and diagnosis.

Inventing and maintaining automation flows that provide the short test time to production.

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Engineering team at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.



Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!

What youll be doing:

You will be in charge of state of the art Design for Test/ATPG flows and implementation.

Take full ATPG ownership end to end on a project, from Arch & planning to pattern generation, verification and post Silicon bring up and diagnosis.

Inventing and maintaining automation flows that provide the short test time to production.

Join our Networking Silicon team as a Senior Full-Chip Design Verification Engineer. In this role, you will be responsible for the development and verification of our next-generation NICs at the system level. You will contribute to the architecture of high-speed communication devices by building advanced simulation platforms and driving full-chip verification execution for the networking solutions powering the worlds most advanced data centers.

What youll be doing:

Full-Chip Verification & Execution: Own complex system-level features by defining verification plans and driving the end-to-end execution.

Software Simulation Development: Architect and code robust software simulation platforms that serve as the foundation for Firmware development and uArchitectural research.

AI-Enhanced Engineering: Accelerate development by leveraging cutting-edge AI coding tools and frameworks.

Global Technical Collaboration: Partner with Architecture, FW, and SW engineering teams across the globe to deliver industry-leading networking solutions.

Our Chip Design group is looking for best-in-class Verification Engineers to join our outstanding Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovative chips, and enjoy working in a meaningful, growing, and highly professional environment where you make a huge impact in a technology-focused company.

What youll be doing:

Verification for chip blocks/entities according to specifications under challenging constraints and with high orientation to performance.

Daily work involves acquaintance with all aspects of chip development: Design, Micro- Architecture, Firmware, Production, and Verification.

Engage in cutting-edge PCIe generation working on latest PCIe gen7.