דרושים » תוכנה » Senior ASIC Frontend Design Engineer

Requirements:
BSc or MSc in Electrical Engineering or Computer Engineering.
8+ years experience in full chip design.
Experience in leading the full-chip level design and successfully taping out multiple intricate SoCs.
Experience in floor planning, integration, signoff methodologies, and signoff tools for hierarchical designs.
Experience with SoC design practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration.
Expert knowledge of the entire backend design flow from RTL to TO.
Experience with STA (Static Timing Analysis) tools like primetime or tempus.
Experience with IR drop tools like Ansys Redhawk or Volta's.
Physical Verification Expert (DRC/LVS).
Strong independent and motivated to learn quickly, hard-working, and is results oriented.
Good social skills and ability to work collaboratively with other teams.
Preferred
Experience with high-speed serial interfaces such as PCIe, DDR, Ethernet.
Familiarity with advanced DFT flows & tools.
Strong proficiency in scripting language, such as, Perl, Tcl, Python, Make, and automation methods/algorithms.

Requirements:
What we need to see:
B.Sc./M.Sc. in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
5+ years of experience in VLSI CAD tool development, with a strong focus on integrating AI/ML techniques into EDA workflows.
Proficiency in Python and at least one AI/ML framework (such as TensorFlow, PyTorch, or scikit-learn).
Hands-on experience with VLSI physical design and familiarity with industry-standard EDA tools (e.g., Synopsys, Cadence).
Knowledge of data preprocessing, feature engineering, and model deployment as applied to VLSI design challenges.
Experience developing and maintaining automation scripts (Python, Perl, Tcl, Make).
Strong analytical skills in evaluating the impact of AI solutions on design quality, performance, and productivity.
Excellent communication skills and the ability to work cross-functionally in a fast-paced environment.
Self-motivation, attention to detail, and a track record of delivering robust solutions to production.

Ways to stand out from the crowd:
Demonstrated experience deploying AI/ML models in production VLSI CAD environments.
Contributions to open-source AI/EDA projects or publications in relevant conferences/journals.
Deep understanding of VLSI design challenges-such as timing closure, power optimization, or yield enhancement-and how AI can address them.
Experience with cloud-based or distributed compute environments for large-scale AI training and inference.
Strong ownership, curiosity, and a passion for continuous learning and innovation.

Requirements:
BSc or MSc in Electrical Engineering or Computer Engineering.
4-7 years of experience in FPGA prototyping or emulation of ASIC/SoC designs
Strong understanding of digital design and RTL (Verilog/SystemVerilog/VHDL).
Hands-on experience with at least one emulation/prototyping platform (Palladium, Protium, Veloce, ZeBu, or FPGA-based)
Good knowledge of synthesis, timing closure, and design partitioning for FPGA/emulation.
Familiarity with verification methodologies and environments (UVM/SystemVerilog/C).
Experience with scripting (TCL, Python, Perl, or Shell) for automation.
Strong problem-solving and debugging skills.
Ability to work in a fast-paced, collaborative environment.
Excellent communication and teamwork skills.
Preferred:
Exposure to software bring-up, driver validation, or firmware testing on emulation.
Knowledge of bus protocols (Ethernet, DDR, etc.).
Experience with debug tools (waveform viewers, logic analyzers, or emulation debug frameworks).
Background in SoC architecture and hardware/software co-design.

Requirements:
What we need to see:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering.
2+ years proven experience in chip design.
Solid hands-on RTL design skills in System-Verilog.
Proficiency in at least one scripting languages like python, bash, tcl.
Great teammate.

Way to stand out from the crowd:
Passion for quality. Experience with delivery to physical design, emulation, firmware and other customers.

Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).

At least 2 years of relevant experience

Proficiency using Python, Perl, Tcl, Make scripting.

Expertise in analysing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes.

Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power required and implementing them through ECOs is required.

Knowledge in process variation effect modelling and experience in design convergence taking into account variations.

Successful track record of delivering designs to production is necessary.

Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.

Ways to stand out from the crowd:

Familiarity with synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Innovus/Tempus)

Experience in methodology definition / flow owner of synthesis / Place and Route/ STA steps is an advantage.

Great teammate.

Ownership, self-learning skills, and ability to work autonomously.

Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering.

7+ years of actual design experience in chip design.

Strong RTL proficiency in SystemVerilog for reading/debugging designs and implementing CDC/RDC-safe structures.

Experience with constraints and timing intent (SDC) and their interaction with CDC/RDC.

Hands-on expertise with industry CDC/RDC tools (e.g., SpyGlass, Questa CDC, Real Intent) and lint/formal where relevant.

Proficiency in at least one scripting languages like Python, bash, Perl, TCL.

Great teammate.

Way to stand out from the crowd:

Passion for quality. Experience with delivery to physical design and other customers.

Requirements:
A degree in Electrical Engineering or a related field.

2+ years of experience in VLSI physical build and integration flows automation.

Strong knowledge in VLSI build/layout and basic programming/scripting skills.

Familiarity with EDA layout tools such as Cadence Virtuoso, Synopsis Fusion Compiler, or Siemens Calibre.

Advantageous to have experience with UNIX, VBA, TCL, or PERL scripting.

Experience or knowledge in power integrity is a plus.

Requirements:
What we need to see: 

BSc/MSc or equivalent engineering degree in Computer Science, Electrical Engineering, or a related field

3+ years of related experience in software development and design 

3+ years of proven experience in Python or similar platform

Excellent knowledge of a version control system (preferably GIT)  

Linux based development

Experience with Software/Hardware products integration

Excellent communication skills with hands-on experience collaborating with global teams

Strong teamwork skills, with the ability to collaborate effectively across cross-functional teams

Ways to stand out from the crowd: 

Familiarity with product manufacturing flows and processes

A highly motivated teammate who always stays up to date with new technologies and test methodologies

Exposure and knowledge around application development, configuration management and automation

Experience in tools/services development. Creativity - find solutions for challenging requirements

Strong leadership skills to drive a project from definition through mass production.

Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent experience.

2+ years of experience.

Proven experience in RTL2GDS flows and methodologies. (advantage)

Knowledge in physical design flows and methodologies (PNR, STA, physical verification). (advantage)

Deep understanding of all aspects of Physical construction and Integration.

Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).

Great teammate.

Requirements:
What we need to see:

B.Sc. in Electrical Engineering or Computer engineering or equivalent experience.

5+ years of practical experience.

Exposure to rtl implementation and coding.

Familiarity with verification tools.

Strong debugging, problem solving and analytical skills.

Strong communication and social skills are required.

Ability to work in a geographically diverse team environment.

Self motivated, independent and target oriented.

Ways to stand out from the crowd:

Prior Design or Verification experience.

Experience in developing sophisticated design blocks.

Integration of design elements to large cluster or full-chip.

Experience in working with back-end on area, power and timing closures.

Scripting ability.