Our technology has no boundaries! We are building the worlds most groundbreaking and state-of-the-art computing platforms for the world to use. Its because of our work that scientists, researchers, and engineers can advance their ideas. At its core, our visual computing technology not only enables an outstanding computing experience, but it is also energy efficient! We pioneered a supercharged form of computing loved by the most fast-paced computer users in the world - scientists, designers, artists, and gamers.

Its not just technology though! It is our people, some of the brightest in the world, and our company's diverse culture makes us one of the most fun, innovative and dynamic places to work in the world! At the center of our culture are our core values like innovation, excellence, determination, and team, which guide us to be the best we can be. We are now looking for a motivated Chip Architect to use your creativity to work on the ConnectX network adapter with the highly inventive and knowledgeable team.

What you'll be doing:

Define the Network Adapter chip architecture end to end from the market requirements through design and all product life cycles (post/pre-silicon, on deployments). Work with related industry standards & customers on deploying your tech.

Collaborate with teams across teams (physical design, logic design, system software, firmware, applications).

Drive Architecture/Software/Hardware co-design and collaboration on features set.

Work on proof of concepts and advance development projects.

Perform research and analysis for current and future architectures.

Craft product design specifications.

Serve as a focal point within the organization and distribute the knowledge that you acquire.

Required ASIC Verification Engineer
Verification Group in a growing group responsible for pre-silicon ASIC Verification of complex chips implementing an advanced modem technology.
As part of the role, you will architect, develop & own blocks / sub-subsystem / system-level verification benches. You will be a major contributor to advanced SV UVM methodologies and to infrastructure development. You will be part of an advanced development flow, using state-of-the-art development & Verification tools and will work closely with the chip architects and RTL / VLSI design teams.
RESPONSIBILITIES
The Verification Engineer will be responsible for different HW blocks at module-level and sub-system level and is expected to:
Have an expert-level understanding of assigned HW blocks as well as a good understanding of the block in the context of whole system.
Communicate with architect, designer, algorithm and other verification engineers to lead complex verification tasks, both on module-level and sub-system testing.
Design complete verification environments.
Implement design in full UVM environment.
Perform full block regressions and collection of functional coverage.

We are looking for a Design Verification Engineer.
In this visible role, you will be responsible for taking part of a SoC verification
process of a large scale SoC.
You will develop verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors.
Apply advanced techniques to achieve verification with the highest quality, productivity, and time-to-market.
You will work closely with the design team to ensure timely delivery of quality designs.
Working with methods to accelerate verification time.
Involvement in Post Silicon Validation.
The position is relevant to all sites: Herzliya, Haifa and Jerusalem

he company develops satellite communication technology radically reducing the cost, size, weight while increasing performance of IoT & user-terminals, payloads and gateway. We are in the process of system definition and design of our next generation Satellite Software Defined Radio (SDR) platforms and are looking for great candidates to handle this complex development.
Job Description:
Develop Physical Layer firmware for satellite standards.
Design of firmware architecture, from top-level down to block-level
Define and write high-level design documents.
Implement DSP Algorithms.
Optimize and debug firmware for performance and throughput.
Development in C, assembler and core specific instructions.