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DRS RADA Technologies , a leading defense company developing and manufacturing life-saving radar systems, is seeking a Complaints & RMA Engineer for its Beit She’an manufacturing facility. The Customer Complaints & RMA Engineer is responsible for the engineering aspects of customer complaints and Returned Material Authorization (RMA) processes. The role involves conducting failure Analysis, performing root cause analysis, leading corrective and preventive actions, and driving continuous improvement of product quality and reliability. The position requires close collaboration with cross-functional teams and customers worldwide to ensure professional, rapid, and effective resolution of quality issues. Responsibilities
* Conduct failure investigations for products returned through RMA processes and customer complaints.
* Analyze product failures using engineering tools and methodologies to identify root causes (Root Cause Analysis).
* Define and lead Corrective and Preventive Actions (CAPA) in collaboration with Engineering, Manufacturing, Quality, and Purchasing teams.
* Prepare detailed failure analysis reports, document findings, and present conclusions to relevant stakeholders.
* Provide engineering ownership of customer complaint investigations through to technical closure.
* Communicate with customers in Israel and internationally, presenting investigation results and providing technical recommendations.
* Support NCR, MRB, and quality investigation processes as required.
* Analyze recurring failure trends and lead initiatives to improve product quality and reliability.
* Coordinate with testing laboratories, suppliers, and subcontractors to perform testing and validate findings.
* Participate in internal and external quality audits as required.
* Ensure compliance with company procedures, quality standards, and applicable regulatory requirements.

We are seeking a Software Embedded Development Engineer to design, develop, and optimize mission-critical embedded software for cloud infrastructure. You will join teams focused on networking, machine learning acceleration, and high-performance computing (HPC), impacting millions of AWS services globally.

Cutting-Edge Technology: Work on custom silicon (e.g., Graviton, ML accelerators) and innovative networking solutions at the intersection of hardware and software.

Growth & Innovation: Benefit from AWSs resources, mentorship programs, and opportunities to publish technical content.

We are seeking a Package Layout Design Engineer to join our hardware team and contribute to the physical design of advanced IC packages for next-generation machine learning and data center ASICs.
In this role, you will execute package layout tasks from floor planning through tape out and manufacturing release, working closely with senior engineers, SI/PI, thermal, and manufacturing teams to deliver production-ready designs that meet performance, density, and reliability targets.

Key job responsibilities
- Execute package layout tasks across the design cycle: die floor planning, bump/pad assignment, RDL routing, substrate design, verification, and tape out release.
- Implement physical designs for advanced packaging architectures including 2.5D interposer, 3D-IC, fan-out wafer-level packaging, and silicon bridge technologies (e.g., CoWoS, EMIB, or similar).
- Support package floorplan development considering die placement, bump maps, power/ground distribution, signal escape routing, and decoupling capacitor placement.
- Perform RDL and substrate routing for high-density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias across multi-layer organic substrates or silicon interposers.
- Support die-level RDL routing and bump planning in coordination with ASIC physical design teams to help co-optimize the die-package interface.
- Contribute to cross-level layout co-optimization across die RDL, interposer/substrate, and PCB levels under guidance from senior engineers.
- Assist in maintaining package stack-up definitions in collaboration with SI/PI and materials engineering teams.
- Run physical verification checks (DRC, connectivity, shorts/opens) and support design closure.
- Follow and help refine package design rules and guidelines, working with OSAT partners and foundries to ensure DFM compliance.
- Collaborate with SI/PI engineers to incorporate electrical constraints into the physical layout - impedance-controlled routing, power plane optimization, and critical net shielding.

Were searching for sharp engineers to lead cutting edge products, re:inventing super computers and deploy our new EFA (Elastic Fabric Adapter) network protocol into the largest public cloud on the planet! starting from the identification and definition of project requirement, defining SW and HW interfaces, feature development and deployment, to operation support on a very large scale.

We're looking for a Design Verification Team Lead - a design verification technical lead that is responsible for complex SoC sub-system, with cutting edge technology for Nitro system SoC, the foundation of AWS's virtualization, networking, and storage offload infrastructure.

It starts at product definition - we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written.

It extends into software - we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack, with particular emphasis on networking workloads such as ENA and EFA.

It reaches into physical design - we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality.

It closes the loop - from spec to silicon, our verification touches every team and every stage of chip development.

Key job responsibilities

- Develop and execute verification plans for IO sub-systems - covering interconnect protocols, peripheral interfaces, and system-level integration with a strong connection to networking flows (ENA/EFA).

- Verify IO sub-system features, including interconnect protocols and various accelerator engines.

- Develop and debug C embedded SW as part of hardware-software integration verification.

- Build and maintain UVM-based verification environments for various clusters and sub-systems.

- Verify ARM advanced interconnect protocols (AMBA CHI/ACE/AXI) ensuring correct coherency transactions, performance verification, and protocol compliance.

- Verify the IO virtualization SMMU/TLB operations, page table walks, translation granules, and memory attributes (cache-ability, share-ability).

- Develop constrained-random and directed test strategies targeting corner cases in IO protocol hazards, coherency races, and system boundary conditions.

- Drive coverage closure using functional coverage models, assertion-based verification, and formal methods where applicable.

- Contribute to performance verification - ensuring micro-architectural implementations meet performance targets alongside correctness.