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Perform thorough Lab characterization/Validation of Serializer/Deserializer (SERDES) IPs, such as PCIeG6 PHYs.
Write Inhouse tools/scripts to characterize the IP.
Manage bench test, debug, and characterization of analog/mixed signal on-chip circuitry (PLLs, Clocks, Data Converters and various I/O Interfaces).
Manage the development of benchtop electrical tests exercising on-chip circuitry through a combination of Joint Test Action Group (JTAG), Universal Asynchronous Receiver/Transmitter (UART), Serial Peripheral Interface (SPI), and other analog interfaces.
Draft and execute scripts to automate tests, extract results, and generate reports using database and investigative tools.

Participate in evaluation of future ASIC designs and general architecture for executing Googles data center networking roadmap, off-the-shelf components, vendor co-developments, custom designs, and chiplets.
Collaborate in developing new layer protocols for data center networking.
Understand how everything interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define performance hardware/software interfaces. Write micro-architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.

Plan the verification strategy, identify the platform to validate reasoning components.
Define the test plan along with the strategy with stakeholders along with the sign off exit criteria.
Plan and execute the Verification of Internet Protocols (IPs) using Dynamic Verification and Formal Verification.

You'll join the Front-End Design team, responsible for all chip design processes from definition and microarchitecture to final product.

Our design engineers engage in every aspect of chip design: definition, design, verification, signoff, and validation through to production.

We apply the latest silicon technologies and processes to build the largest-scale and most sophisticated devices, pushing the boundaries of feasibility.

You'll be part of our Silicon One group, the hub of our ASIC design.

As a member of our team, you'll contribute to driving our groundbreaking next-generation network devices.

Build and mentor a high-performing team of silicon validation engineers, and foster a culture of collaboration, innovation, and technical excellence.
Develop and execute comprehensive validation plans for Google's custom silicon, covering functional, performance, power, and reliability aspects.
Design and build scalable validation test infrastructure, including hardware setups, software frameworks, and automation tools.
Lead the debug and resolution of silicon issues, collaborate with cross-functional teams such as design, architecture, software, and firmware.
Analyze validation data to identify trends, root causes, and opportunities for improvement in silicon quality and reliability.

Youll be working as part of the Silicon One team, interacting with our products groups, both on software and hardware aspects, support developing, based on Leaba architectures, the tomorrow's leading network infrastructure solutions.

Working on implementation and integration, support activities with various new generation products systems developed around the Leaba Silicon. Providing product support, troubleshooting, debug, and resolve the issues, and provide actionable data to our internal team, SW and HW.

As part of this role, you will be working very closely with both internal engineering, SW and HW, and with the products SW team to guide them throughout their system development.

Analyze and debug next-generation our systems products with their technical issues and inquiries.
Provide and be the centric guidance and support for our engineering teams.
Hands-on diagnose and troubleshooting, working on networking protocols for switch/router and infrastructure products.
Work closely with our System product development teams, understanding the applications the data path required and help them by bridging the knowledge on the various aspects related.
Manage and build up with our customers, hands-on debug skills and methodologies.
Transform specialized knowledge of Leaba methodology and state of the art architectures to our System Product engineering teams.

As a Design for Test (DFT) Engineer, you will:
Develop and implement DFT features to ensure high-quality, testable, and manufacturable designs.
Contribute to the full product cycle, from pre-silicon design to post-silicon debug and production qualification.
Work closely with chip architects, design engineers, and verification teams to define and optimize DFT strategies.
Implement ATPG, scan compression, and memory BIST techniques to improve test coverage and efficiency.
Lead debugging and root-cause analysis of silicon failures to improve yield and reliability.
Establish DFT methodologies and best practices to enhance the efficiency of future designs.

Contribute to CPU frontend designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
Propose performance enhancing microarchitecture features with efficiency in mind. Work with architects and performance teams for trade-off studies. Communicate pros and cons of microarchitecture enhancements. Facilitate final decision making.
Deliver designs meeting Power, performance, and area (PPA) goals with production quality.
Become familiar with techniques for at least one processor functional block. Interpret the techniques into design constructs and languages in order to provide guidance to and participate in the performance modeling effort.

Develop and implement strategies for high volume manufacturing of SoC products, including troubleshooting, ATE test coverage optimization, DPPM reduction, Test cost reduction, power and performance assurance, and product data integration and correlation between system, ATE, and System Level Test (SLT).
Drive interactions with wafer fabs and OSATs, own and drive checkpoints for key quality metrics.
Drive volume ramp and mass production through test program releases, volume data analytics, lot disposition, extended test time reduction, yield improvement, and RMA handling.
Collaborate with cross-functional teams across the globe including ATE and SLT Test Engineering, Q&R, Packaging, Supplier Management and Operations to build, deploy, and maintain a high volume manufacturing screening solution.
Support setup and maintenance of test, diagnosis, and yield analysis infrastructure, including RMA support.

Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Apply close coverage measures to identify verification holes and to show progress towards tape-out.

As an Analog Design Engineer, you will:
Design and develop high-speed analog/mixed-signal circuits for industry-leading CMOS process nodes.
Lead all design stages, from architecture definition to final layout sign-off.
Perform circuit simulations, analysis, and debugging to ensure robust performance and reliability.
Collaborate with system architects, digital designers, and layout engineers to optimize circuit performance, power, and area.
Engage in post-silicon validation, debugging, and optimization to enhance circuit functionality.

Execute activities in the design, implementation, and verification of Design for Testing solutions for Application-Specific Integrated Circuit (ASICs).
Develop DFT strategy for hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).
Perform ATPG scan, cover debug and motivate design fixes for coverage and quality improvements.
Perform scan verification at Register-Transfer Level (RTL) and gate level.
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT Scan requirements are met and mutual dependencies are managed.

Our Silicon One team is undergoing rapid growth, and we are looking for a Release Engineer to join our DevOps team.

Join the Silicon One team developing a unified silicon architecture for web-scale and service provider networks. Our silicon team provides an outstanding, unique experience for ASIC and Software engineers by combining the resources offered by a sizable multi-geography silicon organization with the startup culture and breadth of growth opportunities that working in a smaller team can provide.

Your Impact:
You will play a critical role in overseeing the software release lifecycle, ensuring that software products are delivered efficiently, on time, and within scope.
This position requires a blend of software development expertise and program management skills to coordinate cross-functional teams and manage the complexities of software releases.
Youll be the primary contact point between technical teams and stakeholders, providing regular updates on release status, issues, and resolutions.
As a part of your job, youll also work on continuous Improvement: analyzing release processes and performance metrics to identify areas for improvement, designing and implementing automation processes to enhance efficiency and effectiveness.

Define, develop and execute post-silicon validation content on both pre-silicon setups and real silicon platforms in the lab.
Drive silicon from being a chip towards becoming a product.
Debug and investigate issues along cross-functional teams such as Firmware (FW), Software (SW), Design, DV, ARCH and multiple production teams.
Provide quality functional coverage for Google designs.

We are seeking an experienced Python Developer to join our brilliant team. This position is perfect for a creative software Developer who possesses a passion for inventing and designing software, along with a curiosity and desire to learn.
Responsibilities:

* Develop core software: Utilize your software engineering skills to contribute to our dynamically growing organization.
* Join one of our core development teams and collaborate with our brilliant engineers in creating a unique, scalable, distributed Storage system both on-premises and in the cloud.
* Participate in the full product cycle, from definition to resolving critical customer issues.