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We are seeking a motivated Software Engineer to join our team and contribute to the development of a functional simulator for the family of switching and routing ASIC devices. This simulator plays a vital role in accelerating our product development process and ensuring high-quality hardware solutions.

In this role, you will:
Work under the guidance of senior engineers to help implement and maintain components of the simulator based on architecture specifications.
Collaborate with the ASIC Architecture, Software, and Hardware teams to understand requirements and support their use of the simulator as a reference for development.
Participate in troubleshooting, testing, and validating simulator functionalities.
Learn and apply industry best practices in model development and integration.

You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Collaborate closely with the ASIC Architecture team to implement an accurate and efficient software model based on the architecture specifications.

Partner with both Software and Hardware design teams, providing support as they use the simulator as the golden reference for hardware implementation.

Ensure the simulator meets the highest standards of performance, reliability, and usability.

Contribute to defining best practices and methodologies for model development, validation, and integration. 

You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

we are hiring an AML Manager to join our Compliance & Forensics practice.
In this role, you will lead complex engagements for leading financial institutions in Israel and globally-banks, fintechs, NBFIs, payment providers, and investment funds-supporting their compliance with AML/CTF, sanctions, and broader regulatory requirements. You will own delivery, manage teams, build trusted client relationships, and drive high-impact outcomes across governance, controls, and financial crime risk management.
What Youll Do:
Own client engagements end-to-end: lead execution from proposal and scoping through delivery, closure, and commercial management (including billing and collections).
Serve as a strategic advisor to senior stakeholders on AML/CTF, sanctions, and compliance risk-translating regulation into actionable frameworks and practical solutions.
Lead and develop high-performing teams: manage, mentor, and drive delivery excellence across multiple workstreams.
Design and enhance AML/CTF governance frameworks: policies, procedures, controls, risk indicators, monitoring methodologies, and performance measures.
Perform and lead AML/CTF audits and compliance assessments aligned with regulatory expectations and market best practices.
Investigate financial crime cases and analyze suspicious activity/events related to money laundering and terrorist financing.
Oversee regulatory onboarding processes and ongoing compliance lifecycle activities in line with required standards.
Drive technology enablement: support system selection, implementation, and optimization (including rule tuning, scenario refinement, and improvement of existing platforms).
Deliver executive-level trainings and presentations to Boards and senior management, ensuring clear decision-making and strong governance.

As the Physical Design Group Leader, you will provide strategic and technical leadership to a team of engineers, guiding them through the entire chip design lifecycle. You will be responsible for the group's output, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

* Manage and build a world class team managing ASIC design, micro-arch, SDC constraints and integration efforts of the project.
* Translate high level goals to measurable plans and milestones. Lead RTL design, quality checks, and manage schedule for on-time delivery of key IPs.
* Work with verification and physical design teams to achieve high quality design.
* Interface with IP teams and manage schedule and delivery of IPs for successful TO.
* Guide and mentor junior engineers as required.
* Hire and retain tier one engineers and foster teamwork with cross functional collaboration.
* Build a culture of execution excellence coupled with innovation.
* Build a team of hard-working and passionate leaders as we scale.
* Maintain close interactions with NPI, Packaging, DFT, Architecture teams.
* Own power, performance and area optimization of design.

As the leader of the team, you will be responsible for delivering a state-of-the-art functional simulator for the family of routing and switching devices. This simulator is a critical product that streamlines the development process and significantly reduces time-to-market.

In this role, you will:

Lead and mentor and scale the team to 7-10 engineers, fostering a collaborative and inclusive environment
Oversee the design and delivery of a high-performance, reliable, and user-friendly behavioral model for devices
Collaborate closely with cross-functional teams including ASIC Architecture, Software, and Hardware to align goals and ensure seamless execution
Champion engineering excellence by modeling hands-on problem solving and debugging best practices
Guide team members in their professional development with tailored growth plans and regular feedback

Review micro-architecture specifications

Supervise verification team members and provide professional guidance

Implement Verification environment UVM based

Collaborate with Design engineers to resolve bugs and achieve coverage closure

Work with the firmware/Lab teams to verify chip flows

Perform debug, root-cause analysis, and post-silicon validation in the lab

Craft and develop software driving the world's most complex infrastructures
Gain intimate knowledge of world-class silicon and programming models
Work with architecture and design teams to define the next generation of ASIC products being developed

Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab