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our company networking system validation group is growing, and we are hiring a junior switch system Validation engineer. as a member of the team, you will take part in our core network projects which drive the growth of the company, tech and business wise. you'll gain networking and switch u-arch knowledge while helping validate, optimize, and debug devices in different areas like quality-of-service, performance, logic correctness, and ai features. 
you will work closely with logic design, circuit design, and architects to ensure successful product development with aggressive product cycles, in both pre and post silicon stages. 
you should have a good grasp of software development in different fields, such as Python scripting, Embedded software, and device firmware. it's important to have experience in a complex emulation environment and show a strong interest in creating, doing, and improving silicon validation plans. 

what you will be doing: 
work in a combined design and verification team specializing in switch full chip works
understand the switch architecture and build on  TEST plan accordingly 
develop full chip  TEST collaterals/suites, maintain regressions, debug failures and sign-off coverages 
maintain TEST suites to facility emulation and/or silicon platforms checkout as well

seeking an experienced software engineer to join the networking switch sw group, developing the switch operating system (nvos). key role in developing the nvos is critical for next-gen networking tech for hpc data centers. are you passionate about working on innovative technologies? then we want to hear from you!
what you'll be doing:
owning and leading the nvos including development, testing flow and product life cycle.
as a senior software engineer at nvidia, you will use your expertise in C ++ and Python to develop nvos features and support new products.
lead nvos integrations with fw, hardware, and production teams.
support internal and external customers for any nvos related items.

we seek a highly motivated and experienced  system architect specializing in data -center, ai fabric, and ethernet networking to join our team of experts and help shape the future of high-performance ml/ai computing. you will have the opportunity to work on some of the most pioneering technologies and help drive the innovation of our next-generation networks. you will play a key role in defining end-to-end solutions, networking protocols and features, interworking with orchestration systems, and help address new business opportunities in exciting areas. our architects also represent nvidia in open-source projects, technical conferences, and standard development organizations.
what you'll be doing:
explore new technologies and end-to-end solutions for our ethernet networking platforms.
be familiar with data -center and ai fabric network topologies, ai/ml clusters operation and network usage, as well as with the ethernet switch platforms' design and characteristics.
define robust architectures and technical requirements for network operating systems and end-to-end solution offering for ai/ml workloads' needs and highly performing network operations.
lead the work with r&d and validation teams, providing technical guidelines and close support and thorough reviews for detailed designs and TEST plans.
collaboration with architects across various fields, including chip design, firmware, hardware platforms, and system teams.
close work with Product Marketing, program managers, and account managers to ensure the successful execution of projects.
support engagements with key customers, issue patents, publish white papers and blogs, and be proactive in technical forums and industry working groups.
promote innovation through the design and implementation of proof-of-concept (poc).

we are seeking an excellent Software manager to join to nvos  sw group in yokneam ilit. you will have the opportunity to lead a development team responsible for the software of the next-generation networking products while being hands-on with development activities. we drive the data growth of the worlds biggest companies. with dedicated engineers around the globe, the work environment is dynamic, exciting, and fast-paced. are you ready for the challenge?
what you'll be doing:
lead a team of engineers and provide technical guidance to the team of highly skilled engineers. empower the team members to excel and increase team productivity.
lead the design and implementation of new features in the nvos .
drive and facilitate the planning, scheduling, and execution of the project and activities of the team
collaborate with architecture and different software design teams as part of the software development lifecycle.
support internal and external customers for any nvos related items.
gain a deep understanding of networking technology, system debugging, and stacks, as well as the sw/fw relationship.
innovate! bring our networking products to shine in the customers view

we are looking for a 100% hands-on Storage services software engineer to join the block Storage group. you will be a member of a team that builds the next generation block Storage capabilities. you will work closely with a variety of teams and architects including the networking team, and external customers. you will take part in defining the software architecture and implementation of the most advanced Storage services! services that will need to meet extreme performance and scalability demands! we have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform of tomorrow.
at our company, we work, think and learn as a team. we thrive in a deeply strong environment, and we're passionate about a culture that demands innovation and the highest standards. the rewards are sweet and include collaborating with some of the smartest people in the industry, an aggressive compensation plan that rewards top performers, and the opportunity to work on products that transform the way people work and play.
what youll be doing:
100% hands-on coding role in C language, Kernel and userspace
research, design, implement and TEST, new and existing, distributed Storage services and features of our block Storage solution, in both host and dpu environments.
acquire understanding of the algorithms, the technicalities and the interaction with other components across our block Storage ecosystem.
analyze and solve challenging bugs and customer cases in large scale production systems, identifying issues in our or inbox Kernel modules and often in other components. drive new solutions based on any issues that arise

we are continuously improving and evolving the solution to meet the challenging goals. if you find groundbreaking technologies, and next generation products interesting, then this is the team for you. take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
what youll be doing:
you will be in charge of state of the art design for TEST /atpg flows and implementation
take full atpg ownership end to end on a project, from arch & planning to pattern generation, verification and post silicon bring up and diagnosis.
inventing and maintaining automation flows that provide the short TEST time to production

we're looking for a hardware architect for our nic and dpu division. in this position, as part of a small (~10 employees) elite team, you will have the chance to define the architecture of nvidias next generation nic and dpu products. your role will be cross-disciplinary, working with software, asic design, verification, physical design and platform teams to improve performance and debug.
what you'll be doing:
learn and understand the switch u/architecture thoroughly across all aspects and become a source of information for the design and Verification engineers.
define the implementation of the most sophisticated debug features of our next products, balancing architecture requirements with backend, execution, and design considerations.
define the implementation of debug capabilities to support performance validation and improvements
understand our system debug requirements and help define the por of our nic and dpu product line.
face the most challenging full-chip correctness and performance issues, which cannot be handled by the units designers as they require full cross-unit understanding of the chip.
work closely with board and package design to understand the different design limitations: power, di/dt, temperature, signal-integrity etc.
thoroughly understand SOC flows, pcie, ethernet, infiniband and nvlink protocols.

we are looking for a formal Verification engineer for our nvidia networking team!
this is an exciting opportunity to join a hardworking pre-silicon design and verification team, working on groundbreaking switch technologies. we deploy state-of-the art formal verification tools and methodologies to prove design correctness. working in our formal verification team will expose you to a wide range of cutting edge design and technologies. our switch team delivers world class bridge and router solutions for hpc, data -center, network, and Storage markets. we micro-architect, verify, and deliver smart and high bandwidth multi port switches. nvidia has the most sophisticated formal tools and methodologies in the industry, which help us achieve a0 design tapeouts. as part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
what you'll be doing:
in this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
you will work on ambitious designs along with our pre-silicon team and take part in developing the next generation of core technology.
you will work on developing new formal verification methodologies and tactics.

looking for outstanding chip design Verification engineers to join our networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
come and take a significant part in designing and verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company. 
what you will be doing:
join tel aviv group, working in a combined design and verification team which develops phy layer ip within the networking silicon.
build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
work closely with multiple teams within organizations such as architecture, micro- architecture, fw and post-silicon validation.

we are now looking for a senior chip design engineer to join our switch silicon team. as a chip design engineer networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art switch silicon chips. in this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! 
what you'll be doing:
work in a design/verification team which develops core units within the switch silicon.
micro-architecture of rtl verification environments planning for units and modules.
design rtl of units/blocks according to arch. specifications under challenging constraints with high orientation to power, area, and performance.
rtl synthesis, timing, supporting verification, and silicon post to activities.
work closely with multiple teams within organizations such as architecture, u-arch, full chip micro-architecture, be, and fw.

lead a team of 5 engineers in the advanced technologies development
design and implement solutions throughout all layers from high level application, os and driver subsystem to firmware
work on impactful projects involving state-of-the-art high-performance computing hardware and software
provide insight and technical guidance and collaborate with peers from across the company - including software architecture, chip architecture, and engineering departments to improve our future technology
collaborate with nvidia partners and customers

we are now looking for a best-in-class Verification engineer to join our outstanding gpu-networking silicon engineering team. as a dv engineer at gpu-networking group, you'll make a real impact in a dynamic, technology-focused company while being a part of the team that develops the flagship product of todays semiconductor industry - gpu super-chip. 
what youll be doing:
work in a dv (design verification) team that has a global responsibility over deliverable units and clusters to the silicon gpu
integrations and full-chip models
verification of chip blocks/entities according to specifications under challenging constraints
ramp-up and run dv tasks on emulation platform

we are looking for a senior chip design Verification engineer for developing the next generation dft technologies.
as a senior chip design Verification engineer in the dft team , you will verify the design and implementation of our dft technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches, nic and SOC product lines. we are working closely with a wide range of aspects - chip design, backend, verification and production testing. we are working on the most advanced technologies and complex products. our dft solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for verification of the dft design, architecture and micro-architecture using sophisticated verification methodologies.
as a member of our dft verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (testbenches, bfms, checkers, monitors), execute TEST /coverage plans, and verify the correctness of the design.
collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.

looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.