לוח משרות דרושים, לחיפוש זה נמצאו 34,354 משרות

As we expand our presence in Israel, we're seeking a visionary System Validation Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.


Job Description
The mission of this role is to perform system validation for our highly advanced devices, that includes defining strategy, develop tools, innovate, be creative to make sure devices are performing as they should in all aspects, logical, performance, durability, stress and more.

You will be part of the site located at Israel (Haifa - Matam), surrounded with highly experienced and professional engineers who will escort, mentor and support you on your journey in our company.

We are looking for an energetic, creative and highly-collaborative Senior Product Manager to join our strategic and fast growing SaaS Identity Security Platform in the heart of the business, with highest executive attention and company focus. We are looking for Product Managers that are great at:
Leading products/services that are serving multiple other products/services relying on them in addition to providing exceptional service to customers
Collaborating in a cross-functional environment, partnering up with other Product Managers, R&D and other departmental leaders to align and execute product strategies
Performing product and market research on the on-going basis, methodically discovering most important incremental improvements and identifying new opportunities, driving product strategy and business decisions
Thinking ahead while monitoring their assumptions, innovating and improving the product to ensure product growth and best fit to market needs
High level of analytical and quantitative skills - ability to use information/data and various metrics to develop an informed and factual business cases and product decisions
Learning fast new technologically complex domains, thriving in a dynamic environment, able to quickly adapt & adjust to changing demands
Collecting, prioritizing and internally communicating product requirements, defining product features, managing and communicating product roadmap and future releases
Establishing robust SaaS product management practices and contributing knowledge and expertise for building a winning SaaS platform
Able to excite and inspire others to achieve business and product goals, high energy, enthusiastic about building products/services
Working closely with product owners/functional analysts, UX experts and R&D to continuously deliver high-quality value to customers
Constantly engaging with enterprise-scale customers to ensure high level of satisfaction with our product offering, delivering roadmap to individual customers or at events
Focusing on internal customers (R&D teams consuming platform services, professional services and other stakeholders) as well as on external customers
Collaborating with sales, professional services, business development, product marketing, and other stakeholders on a daily basis.

We are looking for an exceptional Senior / Principal Backend Engineer to join our AppSec Platform group, reporting directly to the Group Leader.
This is a highly autonomous, hands-on role for an engineer who wants broad technical ownership rather than a narrowly defined domain. You will work on some of AppSec's most important and challenging engineering problems - spanning high-scale distributed systems, data infrastructure, onboarding and integrations, developer experience, reliability, performance, and AI-driven engineering.
You will frequently operate across team boundaries, take ambiguous problems from idea to production, and lead technical initiatives that have an impact well beyond a single service or team.
We are looking for someone who combines deep backend expertise with strong execution: an engineer who can design the architecture, dive into the code, debug production systems, challenge existing assumptions, rapidly prototype new approaches, and bring others along with them.
Key Responsibilities:
Lead Critical Initiatives End-to-End - Own complex, business-critical engineering efforts from problem definition and architecture through implementation and production, often spanning multiple teams and domains.
Build and Scale the Backbone of AppSec - Design and evolve distributed systems and data infrastructure supporting large enterprise environments and hundreds of millions of entities, while balancing scalability, reliability, performance, and cost.
Stay Hands-On and Raise the Engineering Bar - Write and review production code, solve complex technical problems, and champion excellent architecture, maintainable code, testing, observability, and production ownership.
Drive Performance & Reliability - Identify architectural and operational bottlenecks and lead meaningful improvements in scalability, resiliency, efficiency, observability, and production readiness.
Shape DevEx and AI-Driven Engineering - Improve how engineers build, test, debug, and operate software while leveraging AI, automation, and agentic approaches to accelerate development and unlock new capabilities.

We are looking for a Post-Silicon Validation Engineer with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams.

Key Responsibilities
Perform hands-on post-silicon validation.
Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability.
Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements.
Drive complex issues from initial failure through root-cause analysis and final resolution.
Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries.
Validate PCIe functionality across different generations, platforms, configurations, and operating conditions.
Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests.
Develop automation to improve validation coverage, debug efficiency, and regression testing.

As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.


Key Responsibilities
Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments.
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence.
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments.
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners.
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient.

As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.

You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities
Take responsibility on IR drop analysis and signal/power electromigration (EM) of very complex chip.
Collaborate closely with Physical Design team to insure a full power integrity
Be responsible on IR architecture for timing convergence.
Partner with Package Design engineers to perform Chip-Package co-analysis (CPM).
Understand root-cause analysis for voltage drop violations and EM risks.
Be responsible and go-to person for any IR related issues.

As we expand our presence in Israel, we're seeking a talented Staff/ Principal Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.

As a Staff/ Principal Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified

Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices

Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment