We are looking for a Design Integration Engineer to join our GPU Network Team within the Chip Design Group. This is an exciting opportunity to be part of a growing and expanding team that is shaping the future of GPU networking silicon. Youll work in a dynamic, technology-driven environment where your contributions make a real difference,
with opportunities for growth, learning, and leadership.
Join one of the most desirable employers in the tech industry and help us build the next generation of GPU networking silicon.
What youll be doing:
Drive chip-level integration for advanced GPU networking silicon projects.
Collaborate with architecture, RTL design, verification, FV and physical design teams to ensure seamless integration and optimal performance.
Develop and maintain integration flows, methodologies, and automation to improve efficiency and quality.
Perform RTL synthesis, timing analysis, and support verification and post-silicon activities.
Handle Clock Domain Crossing (CDC) checks and ensure robust design practices.
Work closely with multiple teams across architecture, micro-architecture, backend, and firmware to deliver high-quality silicon.
Contribute to state-of-the-art technologies delivering industry-leading throughput and ultra-low latency for GPU networking solutions.
Requirements: What we need to see:
B.Sc. in Electrical or Computer Engineering
5+ years of experience in chip design, integration, RTL design and/or verification
Strong knowledge of Verilog /System Verilog and RTL design principles.
Hands-on experience with CDC analysis, synthesis, and timing closure.
Familiarity with EDA tools (Synopsys, Cadence, Mentor) and scripting languages (Python, TCL).
Excellent communication skills and ability to work in a collaborative, fast-paced environment.
Ways to stand out from the crowd:
Knowledge of network protocols, HPC, or distributed systems an advantage.
This position is open to all candidates.