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We are looking for talented networking software engineers to develop an innovative new communication stack. Were starting from the ground up, rethinking existing protocols and network accelerators while designing both hardware and software for a new low-latency compute platform. We care about results and insist on doing things right. Our engineers are not siloed into narrow areas; our ideas are cross-fertilized among teams. Our technical backgrounds are diverse and we don't have preconceived approaches or cookbooks, so come and invent! The hardware teams are just a few steps away and really like hearing our ideas. This is a unique opportunity to develop creative solutions from concept to implementation.
Responsibilities
Take part in developing a networking stack from the ground up:
Analyze customer applications and explore creative ways to accelerate them in hardware or software
Find the best ways to process packets on NextSilicons hardware platform
Participate in architecture of future NextSilicon NIC generations
Develop user-space libraries and benchmarks for low-latency communication
Work closely with the hardware teams to offload key features into the next generation of products.

We are seeking an experienced and highly skilled Software Engineer to join our Runtime Software group. In this role, you will drive the development of the full software stack and architecture behind our revolutionary coprocessor. You will be challenged to deliver high-performance, system-wide solutions, requiring a deep understanding of complex architectural trade-offs and distributed systems.
As a core team member, you will design and implement infrastructure that enables our unique hardware to accelerate diverse applications at scale. You will collaborate across disciplines - working with hardware engineers, compiler developers, and system architects - to optimize execution in a massive, multi-process, and multi-threaded environment.
Responsibilities
Design and implement next-generation runtime architectures and infrastructures to support evolving product requirements
Develop environments for the acceleration of massively parallel applications, managing complex process and thread lifecycles
Define development scopes and roadmaps to ensure the successful delivery of robust software features
Partner with hardware and compiler teams to bridge the gap between silicon capabilities and software performance.

We are seeking a talented engineering team leader to lead the team responsible for low-level optimization of AI models and kernels for our unique hardware architecture.
Responsibilities
Lead and mentor a team of engineers developing AI libraries and accelerating AI kernels
Collaborate with hardware, compiler, and device software teams to improve performance.
Develop our optimized AI libraries and related components in the SW stack.
Drive the performance optimization of AI models running on our unique architecture.

We are seeking a talented engineer to work on our AI software stack-specifically, the low-level optimization of AI models and kernels for our unique hardware architecture.
Responsibilities
Develop our optimized AI libraries and related components in the SW stack.
Drive the performance optimization of AI models running on our unique architecture.

Our team is looking for a skilled professional to join the AI software group. In this role, you will focus on our AI kernel compilers, ensuring our hardware delivers peak optimization for sophisticated and custom AI kernels. You will work extensively with various kernel infrastructures, including Triton and CUDA, while collaborating closely with our AI graph compiler teams.
Responsibilities
Develop our AI kernel compilers and related components in the SW stack.
Drive the performance optimization of AI models running on our unique architecture.

We are seeking a top notch software engineer to drive forward the development of the full software stack and architecture behind our revolutionary coprocessor. You will demonstrate creative and critical thinking capabilities and have a genuine passion for tackling complex low-level software issues.
As part of the memory system team, you will work on design and implementation of new and enhanced features of the memory system to support high performance computing and AI applications in the Maverick accelerator runtime environment.
You will work closely with software engineers, hardware engineers, compiler developers and other stakeholders to enable the most efficient execution of applications on a large scale, multi threaded and highly distributed system across multiple disciplines with a deep OS Internals point of view.
Responsibilities
Work on design and implementation of new and enhanced features of the memory system for the Maverick accelerator
Develop a high performance, low latency distributed unified virtual memory management system
Work on system software support for the next generation Maverick system
Define feature development scope and plan for successful product delivery.
Wide system impact through collaboration with software engineers, hardware engineers, compiler developers and other stakeholders.

We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building a complex verification environment from scratch, and defining and executing a test plan. In this role, you will be leading verification from A to Z and will have a critical impact on the company.
Responsibilities
Review specifications and develop attributes, tests, and coverage plans
Define methodology and test benches
Work closely with the verification team to ensure the quality of the product
Build and maintain a smart and scalable verification environment that ties into various systems
Work with the software, design, and micro-architecture teams to understand the functional and performance goals of the products design.

We are looking for a talented and experienced engineer to participate in the physical design of the companys product for leading one of Nextsilison BE projects. This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on product architecture.
Responsibilities
Generate and analyze critical block- and chip-level static timing constraints
Spec and define full chip floor plan, including pin placement, partitions, and power grid
Develop and validate high-performance, low-power clock network guidelines
Perform critical block-level place and route and create designs that meet timing, area, and power constraints
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations
Work with vendors on defining physical design methodologies and assist in flow development for chip integration.