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With the growing demand for traffic bandwidth in datacenters, efficient physical high-speed communication becomes a crucial part of the development of silicon ASCs that serve networking infrastructures. We are looking for a PHY (Physical Layer) Architect for our Architecture team. We are positioning you to a key role to face this challenge and become part of our team, so we can continue developing the best devices in the industry.

Our networking architecture group is seeking for a highly skilled, leading engineer to explore, and define the Physical layer of our products. As a lead engineer, you'll be responsible to define and drive features and have responsibility on the Physical layer architecture. The role will include definition of both the hardware features and the firmware/software that is involved in operating the physical layer communication, with emphasis on the former. We are searching for hardworking, enthusiastic, engineer which has both highly technical skills as well as good personal skills, in order to be able to lead cross groups activities.

What you will be doing:

Lead projects across team, starting from processing requirements and definitions from customers and translating those into detailed technical specification for firmware architecture, system embedded software, user interface and high-level design.

Supervise the implementation of projects by team-leaders / developers / QA, participate in low level design reviews, QA test plans reviews, and keep track of changes and handle obstacles.

Define the architecture of implementing physical layer standards into our ASIC devices.

Involved in standard bodies activities and definition of next generation protocols.

Define features for the phy layer, to exploit interoperability between different generations of communication.

Be involved in product definition and the high-speed protocols that the networking devices will support.

Work closely with multi-functional teams - design, backend, system, marketing, firmware, driver, etc. Provide architecture definitions and as a result converge on key design decisions.

Become focal point for our physical layer networking communication devices.

Our Networking NVLINK group in Israel is looking for an experienced and skilled manager to lead our system/board design team. The team leads the development of GPU networking infrastructure for our next-generation servers focusing on accelerated performance while enabling optimized end to end GPU connectivity. our NVLINK HW team designs innovative end-to-end connectivity solutions for GPU servers. Our products optimize data Center performance and deliver industry-leading bandwidth and scalability. Our products are focused on providing the most optimized power - performance communication solutions for industries like AI, ML, Cloud, Media and Entertainment as well as any other industry that can benefit from our Datastream acceleration.

What you'll be doing:

Build and lead HW design team responsible for delivering HVM high-performance systems

Lead Pioneering Switch System design from concept to mass production

Collaborate and integrate with all HW project subject areas: Board Design, Mechanics, Thermal, PCB Layout, Production, Software/Firmware, RTL and more

Planning the work of your team on multiple simultaneous development projects with a broader leadership team

Managing direct reports, goal setting, mentoring, performance appraisals, career planning and compensation recommendations

Collect, examine, and filter requirements from internal customers such as marketing, software and systems engineering and put together plan of records for next generation switch

Schedule projects, make realistic estimates of outcomes and work to make projects timely and successful for high volume manufacture.

Deep familiarity with the entire design flow including hands-on practice: specification definitions, electrical schematics, component selection, layout guidance, hands-on testing in lab environment, accompanying production and qualification processes, micro-architecture, verification, characterization, design for testability, cost, reliability and more.

Our Networking team in Israel is looking for an expert system/board designer to join the Hardware NVLINK Group. The team leads the development of GPU networking infrastructure for our next-generation servers focusing on accelerated performance while enabling optimized end to end GPU connectivity.

Our NVLINK HW team designs innovative end-to-end connectivity solutions for GPU servers. Our products optimize data center performance and deliver industry-leading bandwidth and scalability. Our products are focused on delivering the most optimized power - performance communication solutions for industries like AI, ML, Cloud, Media and Entertainment as well as any other industry that can benefit from our Datastream acceleration.

What you'll be doing:

Lead Pioneering Switch System design from concept to mass production.

Collaborate and integrate with all HW project fields: Board Design, Mechanics, Thermal, PCB Layout, Production, Software/Firmware, RTL and more.

Project decision maker - Technical focal point.

The position consists of product specification definitions, electrical schematics, component selection, layout guidance, hands-on testing in a lab environment, accompanying production and qualification processes.

We are looking for best-in-class Physical Design Team lead to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

Leading and mentoring Physical Design-Backend team.

Physical design of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part inflows development.

Take part in project definition towards POR, close interaction with other domains such as FE, ARCH.

We are looking for best-in-class Physical Design Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Design of silicon Interposer according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including complex chip designs). Resolving complex FloorPlan and congestion problems.

Daily work involves all aspects of physical design in interposer layout till GDS and Top Die Floor Planning including Bump design

Taking part in flows development.

We are looking for an experienced DFT Engineer to join an exceptional team of DFT experts to develop the next generation DFT technologies.

As a DFT engineer at the networking group, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.

What you'll be doing:

In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.

As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.

Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

We are looking for an experienced engineer with a strong background in ASIC design to join our Chip Design Methodologies & Shared Code team. This team is responsible for establishing design methodologies, developing shared code, providing design guidance, and driving the adoption of new technologies. It plays a key role in ensuring chip design teams operate efficiently and adhere to best practices. This role offers an exciting opportunity to think innovatively and make a significant impact within a dynamic, technology-focused organization.


What You'll Be Doing:

Develop shared design code and solutions to be widely used by the chip design team.

Develop groundbreaking methodologies and innovations to create flawless experience for chip design engineers.

Collaborate with chip design peers and stakeholders across the teams to understand existing problems and form the best solutions and methodologies.

Collaborate with design automation team to provide end-to-end solutions that combine design, verification, simulation and automation.

Get in touch with EDA vendors to learn about cutting-edge tools/technology and apply them into our development process.

Develop training sessions.

Our Networking unit has continuously reinvented itself over two decades. Our high-speed products are leading in the markets with innovative ways to improve speed and bandwidth from one generation to another. Today, we are increasingly known as the place for getting End-to-End High-Speed Ethernet and InfiniBand Solutions. We're looking to grow our company and build our teams with smart people who can join us at the forefront of technological advancement. NVIDIA IC Packaging design team is looking for a Senior IC Packaging Design Engineer to join our package team. and focus on delivering and designing state of the art high-speed Interconnect systems for Supercomputers and Datacenters. This position will collaborate with Technical Package Lead and cooperation with different design teams and development of complex, detailed layout of IC substrates for NVIDIA products.

What you'll be doing:

As part of a IC Packaging design team, you will collaborate to implement high speed and PDN design for ASIC packages.

Develop symbols, pad stack and perform substrate package routing, placement, stack-up, reference plane, power distribution using Cadence APD (Allegro) or SiP tools.

Optimize package pin out incorporating system level trade-offs of pins assignment.

Develop methodologies to improve layout environment, productivity, reliability, and schedule considerations.

In close co-operation with the SI/PI/HW design teams and product teams.

Planning, ensuring stakeholder management and leading projects from start to finish.

We are spearheading the AI revolution and the creation of state-of-the-art accelerated compute platforms for global utilization. Our Network Modeling and Performance Insights group is seeking a skilled and driven Software Developer for the design and development of our infrastructure for a complex networking simulation as a service. In this role, you will be responsible for developing and optimizing our network simulation software, and to enhance its performance and quality. You will work on integrating this infrastructure with cloud computation services for various use cases and ensure the simulation is available as a service for internal and external customers. If you're passionate about tackling intricate challenges and contributing to comprehensive software solutions, we want to hear from you.

What you'll be doing:

Enhance simulation runtime and memory consumption through innovative optimization techniques.

Improve the quality of the simulation as a software product, ensuring robustness and reliability.

Expends the simulation versatility to accommodate new various and complex user use cases and bleeding-edge requirements.

Design and expose the simulation as a service to facilitate easier access for different stakeholders.

Integrate a new simulation management system, making simulated experiments data accessible to all users.

Design and develop a CI/CD infrastructure for our complex networking simulation tool, ensuring efficient deployment and smooth integration processes.

We are looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be developing physical design, STA, Logic eq, Power Integrity flows and methodologies for implementation of networking chips and SOCs.

Work closely with block owners, full Chip STA engineers to assure high quality and timely convergence.

Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.

Additional responsibilities include participating and developing flow and tool methodologies for timing analysis and closure, power and noise analysis, IR-drop, EM and back-end verification across multiple projects.

We are now looking for a best-in-class Senior Chip Design Engineer to join our outstanding GPU-Networking Silicon Engineering team. As a DV Engineer in our GPU-Networking group, you'll make a real impact in a dynamic, technology-focused company while being a part of the team that develops the flagship product of todays semiconductor industry our GPU Super-Chip.

What youll be doing:

Work in a DV (Design Verification) team that has a global responsibility over deliverable units and clusters to the silicon GPU.

Integrations and Full-Chip models.

Verification of chip blocks/entities according to specifications under challenging constraints.

Your daily work will involve all aspects of Design Verification : Planning, Coding, Coverage and Integration.