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AWS Utility Computing (UC) provides product innovations - from foundational services such as our companys Simple Storage Service (S3) and our company Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWSs services and features apart in the industry. As a member of the UC organization, youll support the development and management of Compute, Database, Storage, Internet of Things (Iot), Platform, and Productivity Apps services in AWS. Within AWS UC, our company Dedicated Cloud (ADC) roles engage with AWS customers who require specialized security solutions for their cloud services.
Annapurna Labs, as part of AWS, is looking for an IC Customer Q&R Engineer.
As an IC Quality and Reliability Engineer, you will play a crucial role in ensuring Annapurna Labs' semiconductor products meet customer demands. Your responsibilities will include direct work with Annapurna's customers to jointly debug failures and reduce IC related failures, support RMA analyses
In this role you will be completely exposed to the semi-conductor production flow of all Annapurna Labs products, semi-conductor testing methodologies and FAB process yield improvement activity.

AWS Utility Computing (UC) provides product innovations - from foundational services such as our companys Simple Storage Service (S3) and our company Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWSs services and features apart in the industry. As a member of the UC organization, youll support the development and management of Compute, Database, Storage, Internet of Things (Iot), Platform, and Productivity Apps services in AWS. Within AWS UC, our company Dedicated Cloud (ADC) roles engage with AWS customers who require specialized security solutions for their cloud services.
Annapurna Labs, as part of AWS, is looking for an IC Customer Q&R Engineer.
As an IC Quality and Reliability Engineer, you will play a crucial role in ensuring Annapurna Labs' semiconductor products meet customer demands. Your responsibilities will include direct work with Annapurna's customers to jointly debug failures and reduce IC related failures, support RMA analyses
In this role you will be completely exposed to the semi-conductor production flow of all Annapurna Labs products, semi-conductor testing methodologies and FAB process yield improvement activity.

We are seeking a skilled and driven Algorithm Team Lead to research, develop, and deploy state-of-the-art lidar based techniques that deliver world-class results, enabling the safe development of Autonomous Driving features and Advanced Driver Assistance Systems.
** This position requires on-site presence at our Jerusalem office one day per week.
What will your job look like:
As an Algorithm Team Lead, you will guide a team of talented developers to:
Design, develop, and implement lidar based algorithms in both C++ and python to solve complex problems
Collaborate with cross-functional teams to understand requirements and deliver robust solutions
Conduct research, evaluate existing models and techniques, and propose innovative approaches to improve algorithm performance and accuracy
Optimize existing algorithms for better performance and scalability

As a Quality and Reliability (Q&R) Engineer, you will lead the qualification and long-term reliability of advanced System-on-Chip (SoC) and RF semiconductor products for automotive applications. Youll work across digital and RF domains to ensure robust performance and compliance with industry standards.
What will your job look like:
Define and manage Quality and Reliability specifications, simulations, and qualification plans for SoC and RF die and package.
Plan and execute automotive-grade qualifications per standards such as AEC-Q100, JEDEC JESD22, and IATF 16949.
Design and implement die-level and package-level stress tests.
Select and prepare electrical, environmental, and mechanical test platforms for reliability testing.
Define requirements for Pre-Si Q&R (e.g. ESD, LU, EM, IR drop), Design-for-Test (DFT), electrical characterization, and Post-Si Q&R testing of digital, mixed-signal and RF SoCs.
Collaborate extensively with internal design teams, external subcontractors, and outsourcing partners (OSATs).
Lead failure analysis, reliability modeling, and corrective action processes (e.g., 8D, FMEA, FMEDA).
Document and certify automotive standards compliance, including PPAP/APQP deliverables.

We are a multidisciplinary development team working on a cutting-edge autonomous driving project, at the forefront of automotive technology. The team develops complex ECUs that combine multiple SoCs, low-level firmware, hardware, validation, and automation systems, enabling next-generation autonomous capabilities. We work closely with hardware, system, verification, and automation groups to bring up, debug, and validate advanced automotive platforms from early development stages through production. This is a highly technical, hands-on environment focused on solving real system-level challenges.
What will your job look like:
Debug complex HW/FW and system-level issues in an autonomous vehicle platform
Perform deep root-cause analysis across firmware, hardware, and automation systems
Lead firmware bring-up, integration, and debug of ECUs with multiple SoCs
Debug and support automation systems, including lab automation and FW verification environments
Analyze failures originating from automated test systems and distinguish between FW, HW, and test infrastructure issues
Work closely with HW, system, validation, automation, and architecture teams
Support issues from early development stages through production and field failures
Contribute to firmware debug methodologies and verification strategies
Provide technical leadership and mentoring when needed

We are a multidisciplinary development team working on a cutting-edge autonomous driving project, at the forefront of automotive technology. The team develops complex ECUs that combine multiple SoCs, low-level firmware, hardware, validation, and automation systems, enabling next-generation autonomous capabilities.
We work closely with hardware, system, verification, and automation groups to bring up, debug, and validate advanced automotive platforms from early development stages through production. This is a highly technical, hands-on environment focused on solving real system-level challenges.
What will your job look like:
Debug complex HW/FW and system-level issues in an autonomous vehicle platform
Perform deep root-cause analysis across firmware, hardware, and automation systems
Lead firmware bring-up, integration, and debug of ECUs with multiple SoCs
Debug and support automation systems, including lab automation and FW verification environments
Analyze failures originating from automated test systems and distinguish between FW, HW, and test infrastructure issues
Work closely with HW, system, validation, automation, and architecture teams
Support issues from early development stages through production and field failures
Contribute to firmware debug methodologies and verification strategies
Provide technical leadership and mentoring when needed

our EyeQ Platform Group (EPG) is seeking a motivated Formal Verification Engineer to join our team and contribute to development of hardware verification environments.
This position offers an opportunity to apply formal methods to verify the correctness of various complex digital systems.
This is an exciting opportunity to join a team of talented engineers, working cutting edge technologies in the field of autonomous vehicle.
What will your job look like:
Be the owner of formal verification environment from first draft to sign-off stage
Apply formal methods to verify the correctness of various complex digital systems
Work with HW architects\designers to define assumptions, rules and cover properties
Help define the formal verification methodology and environment to be applied by the team
Explore new Formal methods and Tools
Work with tools like Cadence JasperGold, Verisium manager, Xcelium, Indago
Analyze verification results, identify bugs, and collaborate with engineers to resolve design issues
Develop generic formal blocks\functions of commonly used logic, to be later used off the shelf

we are looking for a Senior Hardware Engineer to join our AV Platform HW Development group in Israel to design the next generation of autonomous driving systems.
What will your job look like?
Responsible for specifying the hardware for our autonomous driving systems
Lead the HW design process: product specification, electrical schematics, component selection, layout, hands-on testing in a lab environment, verification, accompanying production and qualification processes
Define Signal integrity simulations (LPDDR4, MIPI, FPD-link, etc.), perform power integrity (DC drop, PDN AC analysis) and analog simulations (like spice).
Manage the technical interface with our customers to derive the product hardware requirements
Work in collaboration with all the project disciplines: system architecture, mechanical and thermal, software (networking and algorithms), safety and reliability

we are looking for a Senior HW System Architect.
As a Senior HW System Architect, your role will be to work closely with our OEM partners and realize a successful integration of the ADAS to self-driving technology in these platforms.
** This role requires working from our Jerusalem site at least 1 day per week. It also offers the flexibility to work part-time from our other sites, subject to seat availability.
What will your job look like?
Lead end-to-end life cycle of the System architecture - from analyzing OEMs (customers) technical requirements to HW architecture definition, development and verification to ensure integration ofproducts into the vehicle platform.
Work in close collaboration with various groups including algo, HW design, verification, SW architect, Mechanics, and simulations.
Provide architectural guidance and tradeoff recommendations throughout the whole design process from concept through production.
Responsible for the main components selection and technical evaluation (trade-off between cost/performance etc.)
Provide practical system architecture definition to board designers and SW/algo by managing system external Interconnects and internal interfaces, SoC, MCU, definitions and optimization (based on OEMs requirements and other constraints)

The SOC verification group owns the important and challenging job of verifying chip. It is involved from product specification to final SOC delivery, and involves all the system components.
The group is made up of few of the best verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams.
What will your job look like:
You will manage a team of 5 engineers
You'll be responsible for Pre-Silicon system-level verification of the most cutting-edge AI accelerators and technologies in the automotive field.
Define the TestPlan, develop and run tests on simulation/emulation environments, develop test environment and verification collaterals.
You'll have a broad effect on our unique product from the very beginning of the process.

In your role as a senior PHY Algorithms Development Engineer, as part of our Connectivity Group, you will be part of a world-class group that pioneers design and development of Physical Layer algorithms for wireless communication systems for our products. We live in a mobile and device driven world where knowledge of the physical world around us is needed. We rely on this knowledge to get around, to learn about our environment and to enable spectacular new features for custom applications. We are meeting those needs as robustly and as creatively as possible and is interested in people who want to help meet that commitment. The success we are targeting will be the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking of old problem in new ways. If that sounds like the kind of environment that you find intriguing, then let's talk.

We are looking for a candidate who can innovate and integrate signal processing technologies for solving novel and diverse sets of problems in various wireless communication and sensing technologies:
- Develop communication signal processing algorithms for best-in-class implementation of various wireless standards.
- Conduct basic research of existing solutions in literature.
- Involvement in block level spec definition.
- Perform mathematical analyses of the given problem and its proposed solutions.
- Implement floating-point simulations to prove spec compliance of suggested solutions.
- Implement fixed-point modeling and simulation to allow performance sign-off and RTL bit-exact development .
- Write detailed design documents that will enable implementation of algorithms by other teams specializing in either RTL design or DSP firmware coding .
- Optimize and fine-tune the system for spec compliance on silicon in an RF lab environment.

In your role as a senior PHY Algorithms Development Engineer, as part of Apple Connectivity Group, you will be part of a world-class group that pioneers design and development of Physical Layer algorithms for wireless communication systems for Apple products. We live in a mobile and device driven world where knowledge of the physical world around us is needed. We rely on this knowledge to get around, to learn about our environment and to enable spectacular new features for custom applications. Apple is meeting those needs as robustly and as creatively as possible and is interested in people who want to help meet that commitment. The success we are targeting will be the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking of old problem in new ways. If that sounds like the kind of environment that you find intriguing, then let's talk.

We are looking for a candidate who can innovate and integrate signal processing technologies for solving novel and diverse sets of problems in various wireless communication and sensing technologies:
- Develop communication signal processing algorithms for best-in-class implementation of various wireless standards.
- Conduct basic research of existing solutions in literature.
- Involvement in block level spec definition.
- Perform mathematical analyses of the given problem and its proposed solutions.
- Implement floating-point simulations to prove spec compliance of suggested solutions.
- Implement fixed-point modeling and simulation to allow performance sign-off and RTL bit-exact development.
- Write detailed design documents that will enable implementation of algorithms by other teams specializing in either RTL design or DSP firmware coding.
- Optimize and fine-tune the system for spec compliance on silicon in an RF lab environment.

This role is for an analog layout IP lead who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of silicon development from definition to high quality production.

Senior Layout Leads are responsible for delivering Analog Mixed-Signal IP in an SOC flow. They collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs.
As a member of the AMS layout team you will be responsible to deliver Physical Design Verification clean layout, this includes the following:
Crafting complex layout for mixed signal, and analog circuits in deep SubMicron CMOS technologies.
Reviewing and analyzing floor-plans and complex circuits with circuit designers.
Running complete set of design verification tools available on AMS blocks.
Working with the circuit design team to plan/schedule work and negotiate any necessary layout trade-offs as needed.
Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout.
Exceeding engineering specifications and expectations by working closely with the circuit design team.
Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.

We are hiring a Principal Algorithms Solution Architect to lead innovation in algorithm design and system architecture, delivering transformative solutions in graphics, vision, and AI for our next-generation iTero scanners.
The role is located in Petah Tikva or Caesarea
Key Responsibilities:
Lead and execute cutting-edge algorithmic challenges, driving knowledge and breakthroughs across the company.
Play a pivotal role in shaping our algorithmic strategy and influencing performance outcomes.
Provide guidance, mentorship, and leadership to teams, ensuring successful delivery across multiple projects.
Apply advanced troubleshooting skills and collaborate with R&D and Product teams to resolve complex technical issues and ensure system reliability.
Partner with stakeholders to anticipate future challenges and design innovative solutions.
Participate in all phases of the algorithm development cycle, from concept through deployment.
Identify risks in algorithm and system design and propose effective solutions.
Evaluate existing solutions and recommend improvements to enhance efficiency, scalability, and robustness.
Consistently demonstrate innovative thinking, systemic understanding, and strong cross-team collaboration.
Maintain a strong leadership presence, fostering accountability, growth, and high performance across the organization.