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We are looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be in charge of developing physical design, synthesis, STA and Logic eq methodologies for implementation of networking chips and SOCs.

Work closely with block owners. full Chip STA engineers and project managers to assure high quality and timely convergence.

Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.

Additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.

We are looking for a talented Signal Processing and Communications Engineer to bridge the gap between simulation and real-world performance for high-speed wireline communication links. In this role, you will analyze lab results to refine development simulators and align them closely with actual SerDes performance, ensuring future designs are driven by real measurements, not just theoretical models. You will play a critical role in optimizing current designs for faster, more reliable chip bring-up and shaping the architecture of next-generation solutions. As part of the algorithm team, you will be actively involved in debugging unique and complex phenomena observed in the lab, working alongside post-silicon engineers to directly influence product performance. Separately, this role also provides a rare opportunity to gain broad system-level understanding, offering visibility into how the SerDes integrates and interacts within the larger chip architectureinsight typically beyond the standard algorithmic scope.

You will collaborate closely with analog and digital designers, signal integrity experts, and other cross-functional teams to ensure simulation models and lab results accurately represent real-world system behavior. If you are passionate about solving complex signal processing challenges and working at the forefront of technology, we want to hear from you.

What you will be doing:

Develop HW tools and flows to improve lab debuggability and visibility.

Correlate simulation results with lab measurements to improve model accuracy.

Work closely with cross-disciplinary teams to ensure accurate and reliable model representation.

Find performance bottlenecks

Characterize and evaluate analog and digital blocks in the lab to contribute to the DSP architecture and modeling strategies for next-generation SerDes designs.

We are seeking a highly skilled and expert Verification Lead to join our PCIe Firmware team. In this role, you will be responsible for supervising the verification plans, monitoring their execution within the teams, guiding engineers through the verification implementation, and tracking coverage, Coverity, and other relevant statistics. You will be joining a team dedicated to developing groundbreaking technology and building the core technology of next-generation devices across various fields, including low-level C layer between hardware and firmware, C++ verification environment, automation challenges, and Python testing environment.

What youll be doing:

Develop and lead verification plans, ensuring they are driven effectively within the teams.

Provide guidance to engineers on verification implementation within the verification environment.

Monitor coverage, Coverity, and other statistics to ensure comprehensive verification and optimization of next-generation NVIDIA products.

Work closely with firmware design, chip design, software, and architecture teams to define and craft both legacy and new low-level firmware flows.

Enhance methodologies and automated processes to improve efficiency and effectiveness.

We are looking for a Chip-Design Verification Engineer to join our Switch Silicon team. As a Chip Design Verification Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a design and verification team that develops the front-end design for the Switch silicon and the GPU.

Develop verification components and reference models, as well as verify and simulate chip blocks according to specifications under challenging constraints with a high orientation to power, area, and performance.

Work closely with multiple teams within organizations such as Architecture, Micro- Architecture and FW.

We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation Infiniband and NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today, such as car and Pharmaceutical. As a high-performance system architect, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.

What youll be doing:

Define the Infiniband and NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).

research of various solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.

The architect should have experience in developing models for simulations, analyzing simulation results and development of optimization algorithms.

Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

We are looking for a ASIC SOC Design Engineer.
Responsibilities:
Be a significant part of the SoC Silicon team, developing next generation IOT and AI chips.
Take part in all aspects of digital design from architecture and specification, RTL design and verification.
Close collaboration with the Physical Design team, and supporting SW and Production teams.
Contribute to the development of a very complex state-of-the-art technological project.
Integration of sophisticated sub-systems.

We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation Infiniband and NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today, such as car and Pharmaceutical. As a high-performance system architect, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.

What youll be doing:

Define the Infiniband and NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).

research of various solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.

The architect should have experience in developing models for simulations, analyzing simulation results and development of optimization algorithms.

Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

We are looking for best-in-class Chip Design Engineer to join our outstanding Networking Silicon engineering team. We are developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you will be doing:
Join accelerators IP group in Beer-Sheva/ Tel-Aviv, working on RiscV platform unit and cache coherence IP.
design for chip blocks according to specifications under challenging constraints and with high orientation to power, area and performance.
Daily work might involve any or all aspects of chip development: uarch , Design.
Work closely with Firmware and other groups around the globe.

We are looking for a System validation site manager.
Responsibilities:
- Lead and manage the system validation group at the IL site.
- Develop and implement validation strategies and plans for Sony products.
- Oversee the operation and maintenance of worldwide automation testing systems.
- Design, implement, maintain, and run automation campaigns on various setups on a weekly/monthly basis.
- Analyze and debug test results, report results and issues into Sonys data systems.
- Ensure compliance with industry standards and regulatory requirements.
- Collaborate with cross-functional teams to ensure seamless integration and validation of new products and features.
- Provide technical guidance and mentorship to team members.
- Improve efficiency by using AI technology
- Design and implement quality procedures

We are looking for best-in-class Chip Design Engineer to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in verifying our ground-breaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What youll be doing:

Work in a combined design and verification team that develops front-end design for the Switch silicon, GPU and HCA.

Plan and Design Verification units/blocks according to Arch & Micro arch specifications under challenging constraints with high orientation to power, area, and performance.

Work closely with multiple teams within organizations such as Architecture, Micro-Architecture, and FWinteraction with organization-wide groups.

We are now looking for a Chip Design Manager to join our Network Adapter Silicon group. As a Chip Design Manager in our Networking business unit, you'll join a group of passionate professionals to design, lead the implementation of the next generation state-of-the-art Networking Silicon chips . In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What youll be doing:
Lead a team of design and verification engineers that develops core units within the NIC silicon.
Be responsible for the delivery of complex RTL units and its verification.
Work closely with multiple teams within organizations such as Architecture, Full chip Micro-Architecture, BE, and FW.

We are excited to announce that the team is undergoing rapid growth, and we have opened multiple positions for Junior C++ Software Engineers!
Location: Caesarea, Israel
Your Impact:
You'll develop Core Software technologies at the heart of tomorrow's leading infrastructure solutions, tackling the entire range of challenges from user-facing API-s, through high-level algorithms, all the way down to firmware.
In this role, you will:
Craft and develop software driving the world's most complex infrastructures
Gain intimate knowledge of world-class silicon and programming models
Work with architecture and design teams to define the next generation of ASIC products being developed

We are looking for a PHY Validation Engineer.
What You'll Do:
Youll be joining the post silicon validation team in PHY system group Silicon One group as part of the silicon development .
Our team deals with PHY and system aspects of the SerDes communication IP: PHY FW, calibrations, system definitions and operations and post-silicon validation including developing the automation infrastructure and tools.
We use latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.

Join the team in developing a unified silicon architecture for web-scale and service provider networks.
the team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, café, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide.
Your Impact:
Define devices and deliver specifications to other development teams.
Work with internal and external customers to understand and define current and future requirements.
Innovate at all levels to deliver market-first features and solutions.
Conduct in-depth research to shape the architecture of next-generation networking devices.
Contribute to full-chip integration and cross-functional collaborations to enhance design methodology.
Participate in the definition and analysis of networking system solutions, ensuring they meet market and technical needs.

Join the Silicon One PHY System Team, a key part of our silicon development. You'll be at the forefront of defining, implementing, and validating advanced PHY and system solutions for next-generation network devices.
Your responsibilities will include:
Defining features for future devices utilizing cutting-edge silicon technologies.
Developing and optimizing PHY firmware and calibration processes.
Driving system-level definitions, operations, and post-silicon validation.
Collaborating with cross-functional teams to ensure high-quality deliverables.