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23/06/2026
Location: Yokne`am
Job Type: Full Time
We are looking for a Formal Verification Engineer for our NVIDIA Networking team!

This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking NIC technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies. Our NIC team delivers world class CPU interface and offload solutions for HPC, data-center, network, and storage markets. We micro-architect, verify, and deliver the best and most widely used high BW ethernet and IB NICs in the industry. NVIDIA has the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tapeouts. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.

What you'll be doing:
In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of NVIDIA's core technology.
Learn state of the art formal methodologies and advance your expertise in communication protocols and hardware implementations.
Requirements:
What we need to see:
BSc in Electrical/Computer Engineering or MSc in Mathematics, or equivalent experience.
1-3 years of relevant experience.
Excellent analytical, logical reasoning and problem-solving skills.
Strong debugging and analytical skills.
Strong communication and interpersonal skills are required.

Ways to stand out from the crowd:
Formal verification work experience.
Knowledge of digital logic.
This position is open to all candidates.
 
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23/06/2026
Location: Yokne`am
Job Type: Full Time
We are looking for an experienced Team Lead for the NIC FW verification infrastructure team. In this role, you will lead the verification infrastructure - ensuring testing infrastructure stability, scalability, and continuous improvement - while guiding the development of advanced modules and methodologies. You will be responsible for driving the teams technical direction, supporting the evaluation of data and control path for new features, and ensuring high-quality deliverables that meet the expectations of industry-leading customers. As a leader, you will mentor and grow a team of engineers, foster a culture of ownership and execution, and collaborate closely with our networking NIC FW teams.

What you will be doing:

Lead and drive team execution end-to-end, combining managerial ownership with hands-on technical contribution - including ownership of the verification testing domain, its flows, coverage and the regression cycle.

Develop deep expertise in our technologies, with a strong focus on FW functionality with corresponding interfaces with HW and SW.

Drive team execution by setting clear priorities, removing blockers, and ensuring high-quality, timely delivery - while maintaining a high bar for technical excellence and clearly communicating priorities, trade-offs, and status to stakeholders.

Define and continuously improve testing methodologies, including leading retrospectives for missed bugs to identify gaps - driving actionable changes to test coverage, flows, and verifiers.

Act as a technical leader within the team, contributing to design discussions, mentoring engineers, and actively participating in high-level design and code reviews.
Requirements:
What we need to see:

B.Sc. in Software Engineering, Computer Engineering, Electrical Engineering, or Computer Science.

3+ years of experience in an engineering management or team leadership role, with a strong hands-on technical background. 6+ overall years of experience as an engineer.

Strong coding skills with deep understanding of OOP principles and software design.

Ability to operate effectively in a fast-paced, dynamic environment, balancing execution with continuous improvement.

Demonstrated leadership qualities - ownership, initiative, problem-solving mindset, and the ability to drive results independently and as part of a team. Excellent verbal and written communication skills in English, with the ability to clearly articulate priorities and align with stakeholders.

f
Ways to stand out from the crowd:

Deep familiarity with c++.

Familiarity with regression concepts, testing flows, and CI practices.

Knowledge of Networking protocols.

Working with Git, Gerrit, Jenkins, Docker.

Experience in working in an agile approach.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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22/06/2026
Location: Tel Aviv-Yafo
Job Type: Full Time and Hybrid work
Required Micro-Architect
Description
A global leader in control systems for quantum computing, a field on the verge of exponential growth.
Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands.
At the core of the company lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers.
Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field.
Join our cutting-edge hardware development team as Micro-Architect and play a key role in defining and implementing the micro-architecture of advanced digital logic components.
What You'll Do:
Define and develop micro-architecture for complex logic blocks - from concept through high-quality RTL implementation
Collaborate closely with architecture, verification, design and software design teams
Write clear and detailed design specifications and drive architectural trade-off analysis
Optimize for performance and area
Contribute to innovation, methodology improvements, and technical leadership within the team.
Requirements:
B.Sc. or higher in Electrical Engineering, Computer Engineering, or related field- Must
8+ years of experience in RTL design using Verilog/SystemVerilog- Must
Proven experience in designing micro-architecture for complex systems
Strong system-level understanding and problem-solving skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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22/06/2026
Location: Tel Aviv-Yafo
Job Type: Full Time and Hybrid work
We are looking for an excellent design engineer to join our team and build our state-of-the-art control and orchestration platform. We are looking for a highly talented and motivated person, who is a real team player and which can collaborate closely with engineers from other disciplines and quantum physicists
Responsibilities:
Designing a configurable and very low-latency challenging RTL
Bringing the state-of-the-art FPGA to its limits with regards to logic & timing optimization
End2end ownership of the entire coding process (Arch->uArch->Design->Implementation)
Learning system and SW requirements for proper implementation of HW-SW interface.
Requirements:
BSc in electrical/computer engineering or relevant military background
At least 4 years of experience
Proven track record in RTL coding with System Verilog
Experience with System Verilog
VCS, Vivado - Advantage.
This position is open to all candidates.
 
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22/06/2026
Location: Tel Aviv-Yafo
Job Type: Full Time and Hybrid work
We are looking for a highly experienced a hands-on Compiler Engineer who embodies ambition and positivity.
Someone who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfill the evolving needs of our expanding customer base.
Responsibilities:
Develop our compiler from a proprietary quantum language to a proprietary processor tailored to realize and accelerate quantum computing.
Take on complex optimization challenges at the core of our unique compiler, focusing on real-time applications, hybrid quantum/classical algorithms, and parallel processing.
Conduct rigorous testing, debugging, and profiling to ensure the performance and correctness of compiler outputs.
Hands-on development and debugging of software to optimize the utilization of limited hardware resources, enabling the scaling of quantum computing systems and improving quantum algorithm performance on our cutting-edge quantum orchestration platform.
Collaborate closely with hardware, software and architecture teams to ensure seamless software-hardware integration, directly enhancing system capabilities and performance.
Requirements:
At least 5 years of hands-on programming experience - Must.
BSc. in Computer Science, Computer Engineering, Mathematics, or any relevant scientific field (advanced degrees are an advantage) - Must.
Experience in computer architecture, assembly language, and low-level programming concepts - Advantage.
Experience working in a multidisciplinary environment - Advantage.
Familiarity with MLIR/LLVM - Advantage.
A motivated and resourceful problem solver with a passion for tackling complex technical challenges, especially in hardware-oriented environments.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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22/06/2026
Location: Yokne`am
Job Type: Full Time
We are looking for a talented and experienced Team Manager to join our CAD Sign-Off group, sitting at the intersection of CAD development and circuit engineering. Our team drives both the development of CAD flows and tools as well as circuit studies and design methodologies, supporting world-class silicon sign-off for our most advanced chips. The role combines internal development work with close collaboration across multiple groups worldwide. You will lead a team responsible for tracking and executing these activities end-to-end, ensuring quality, alignment, and delivery across all fronts. Come be part of a highly professional, impactful environment where your leadership shapes the way we design and sign off our chips.

What you'll be doing:

Own the tracking and execution of team activities spanning both internal CAD flow development and circuit-level studies and design methodologies.

Lead and coordinate engineers working across CAD sign-off, circuit analysis, and design methodology domains.

Drive collaboration with chip design teams, full-chip engineers, and other CAD and design groups globally, ensuring timely and high-quality sign-off convergence.

Serve as a key interface between the team and other groups, aligning priorities, sharing methodologies, and driving cross-group initiatives.

Identify risks and bottlenecks early, propose mitigation plans, and keep projects on track.

Foster a culture of ownership, technical excellence, and continuous improvement within the team.
Requirements:
What we need to see:

B.Sc./M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience.

8+ overall years of experience in engineering or software development, with a solid technical foundation in CAD, EDA, or circuit design environments.

3+ years of experience in team management roles in CAD or Backend design domains.

Proven ability to track, manage, and complete complex engineering activities across multiple workstreams.

Strong organizational skills, attention to detail, and excellent written and verbal communication.

Demonstrated ability to work effectively both within a focused engineering team and in cross-group, cross-site collaborative settings.

Ways to stand out from the crowd:

Background in circuit design or analysis - familiarity with sign-off domains such as STA, power integrity, IR-drop, or EM is a strong plus.

Prior experience in a formal management or team lead role.

Experience conducting or reviewing circuit studies, feasibility analyses, or design methodology evaluations.

Familiarity with EDA tools such as PrimeTime, RedHawk, or similar sign-off platforms.

Track record of successful collaboration across multiple engineering teams or organizations.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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22/06/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
Join us and become a pivotal part of our Networking Silicon engineering team in Tel Aviv, Israel. We are renowned for developing the industry's top high-speed communication devices, known for their outstanding efficiency and minimal latency. This role offers an outstanding opportunity to be involved in groundbreaking projects, collaborating with versatile experts to foster innovation and excellence. As a Senior Chip Design Verification Engineer, you will be immersed in a dynamic and encouraging environment where your efforts will have a meaningful impact.

What you'll be doing:

Play a crucial role in developing our next-generation chip controller.

Engage in building and verification tasks within a challenging, multi-disciplinary context.

Collaborate closely with cross-functional teams to advance our networking and GPU networking chips and systems.

Drive the implementation of sophisticated verification environments to ensure flawless functionality.
Requirements:
What we need to see:

B.Sc. or M.Sc. in Computer Engineering, Electrical Engineering, or Communication Engineering.

0-4 years of proven experience in ASIC Verification.

High proficiency in English.

Demonstrated ability to work well within a team, exhibiting strong communication and interpersonal skills.

A proactive and ambitious approach, with strong attention to detail and a dedication to excellence.


Ways to stand out of the crowd:

Background in Specman.

Knowledge in HDL (Verilog/VHDL).

Knowledge in industry Standard Protocol such as I2C, GPIO and AMBA.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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21/06/2026
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be in charge of developing full-chip physical design methodologies, Physical Verification development and support through all the projects, Tapeout activities for implementation of networking chips and SOCs.

Work closely with Full Chip Layout owners and block owners, project managers to assure high quality and timely convergence.

Come up with unique and creative solutions to the state of the art FCL physical design problems that are needed for our chips.

We expect you to run, debug, and approve Physical Verification flows across multiple projects, ensuring strict adherence to our high standards.

Participating and developing flow and tool methodologies for fullchip, physical design verification across multiple projects.
Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).

You should have at least 5+ years of hands-on Full-chip layout and Physical Verification experience, demonstrating your proven expertise.

A strong background in Physical Verification methodology, including DRC / LVS / ANT / ERC / DFM in advanced process nodes is necessary.

Proficiency using Python, Tcl, Shell, Make scripting.

Experience in Linux environments.

AI tools orientation or alternatively a desire to learn.

Familiarity with physical build EDA tools, including Synopsys (ICC2/FC) and Cadence (Innovus).

Familiarity with Physical Verification tools: Synopsys (ICV), Siemens (Calibre)

Self-motivation, attention to detail, and good interpersonal skills.


Ways to stand out from the crowd:

Experience with data collection and analysis

Experience in methodology definition / flow owner of Full-chip / Place and Route

Great teammate.

Ownership, self-learning skills, and ability to work autonomously.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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21/06/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
As an AI/ML Solution Engineer in the AI-Native Development team, you will design and build AI-powered development pipelines, evaluate ML approaches for code generation and review, and drive the adoption of AI-assisted software development across the organization. You will work at the intersection of machine learning and software engineering - selecting the right models, feedback strategies, and evaluation frameworks to make AI-generated code reliable, high-quality, and trustworthy.

What you'll be doing:

Drive architecture, applied research, and hands-on development by defining and building AI-native software engineering solutions.

Design and build AI-powered development pipelines - from code generation and automated review to feedback loops and evaluation systems.

Evaluate and select ML approaches for specific problems: when to use LLM prompting vs. fine-tuning (QLoRA), classical ML (random forest, linear regression) vs. reinforcement learning, RAG vs. structured extraction.

Architect feedback and evaluation systems that measure and improve AI output quality over time.

Review and refine AI solution architectures - evaluate design decisions, identify weaknesses, propose alternatives with reasoning.

Lead proof-of-concept development to validate new AI/ML approaches for development tooling.

Collaborate with the core team to define risk-based development levels and calibrate AI review depth per level.
Requirements:
What we need to see:

Hold a M.Sc. or Ph.D. in Computer Science, Electrical or Computer Engineering from a leading university (or equivalent experience).

5+ years of industry experience (or equivalent) in software architecture, hands-on development, AI/ML, applied research, or related fields.

Strong background in software or solution architecture, applied AI/ML research, or hands-on development of production-grade AI systems.

Industry experience building and shipping AI-powered tools or ML pipelines (not just training models - end-to-end delivery).

Strong understanding of LLM capabilities and limitations - prompt engineering, fine-tuning, RAG, agent architectures.

Experience with at least two of: reinforcement learning, classical ML, NLP/information retrieval, evaluation framework design.

Strong understanding of AI development and evaluation pipelines.

Can reason about trade-offs: when to use which approach, with real reasoning backed by shipping experience.

Strong programming skills (Python required; familiarity with ML frameworks - PyTorch, HuggingFace, etc.).

Ability and flexibility to work and communicate effectively in a multi-national, multi-time-zone corporate environment.

Ways to stand out from the crowd:

Experience with LLM-based code generation, code review, or developer tooling.

Familiarity with eval frameworks and feedback loop design (online and offline evaluation).

Experience with AI agent orchestration (multi-agent systems, tool use, planning).

Shown research track record (publications, open-source contributions).

Knowledge of AI-assisted development tools and their underlying architectures.
This position is open to all candidates.
 
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21/06/2026
Location: Yokne`am
Job Type: Full Time
This role brings together horizontal ownership across engineering process, security coordination, developer productivity, DevOps, integration, and product usability. The leader will define clear operating models, remove execution friction across organizational boundaries, and ensure that DOCA software, tools, and workflows are robust, secure, integrated, and intuitive from development through deployment. The ideal candidate is comfortable leading people, working across engineering groups, understanding complex system-level software, and translating operational, security, integration, and usability challenges into clear priorities, ownership, and measurable improvements.

What you'll be doing:

Lead the DOCA Process and Productivity function, including cross-organizational process execution, DevOps, integration, UX/usability, security process coordination, and developer productivity initiatives.

Own and improve operating mechanisms across DOCA R&D, QA, release, security, integration, DevOps, lab infrastructure, and partner teams.

Serve as the Security Point of Contact for the DOCA framework, driving secure development workflows, vulnerability handling, security reviews, incident management, and alignment with NVIDIA security requirements.

Drive improvements in build, validation, release readiness, automation, CI/CD, lab workflows, deployment experience, documentation, and end-to-end engineering productivity.

Lead, mentor, and grow teams while helping the organization make multi-team workflows more predictable, transparent, secure, automated, accountable, and efficient.
Requirements:
What we need to see:

B.Sc. or M.Sc. in Computer Science, Computer Engineering, Electrical Engineering, Industrial Engineering, or equivalent experience.

15+ overall years of relevant professional experience in software engineering organizations, engineering operations, DevOps, integration, technical program management, process management, or system software execution roles.

Minimum of 7 years managing R&D engineers.

Proven people leadership experience, including leading teams, mentoring managers or senior engineers, setting direction, and building an operational or engineering productivity function.

Strong technical understanding of complex software systems, Linux environments, infrastructure software, integration flows, release processes, and system-level debugging.

Experience improving engineering workflows such as integration, release readiness, CI/CD, issue handling, requirements flow, secure development, vulnerability handling, or inter-team handoffs.

Excellent communication and cross-functional leadership skills, with the ability to align engineering leaders and turn ambiguous operational, technical, or usability problems into clear actions and priorities.

Ways to stand out from the crowd:

Familiarity with DOCA, BlueField DPUs, SmartNICs, cloud infrastructure, developer frameworks, data center infrastructure, or large-scale system software.

Experience leading DevOps, integration, lab, release, engineering productivity, security process, or UX/usability functions in a complex R&D organization.

Proven success improving out-of-box product experience, provisioning, deployment workflows, documentation quality, automation, or customer-facing integration flows.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
21/06/2026
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for best-in-class Senior Chip Design Verification Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in designing and verifying our groundbreaking and innovating new chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.

What you'll be doing:
Take a crucial part in developing our next-generation chip controller and boot.
Design and verification with challenging multi-discipline context.
Take part in the development of all our networking and GPU networking chips and systems.
Requirements:
What we need to see:
B.SC./ M.SC. in Computer Engineering/Electrical Engineering/Communication Engineering.
5+ years of validated experience in ASIC Verification.
High Level of English.

Ways to stand out from the crowd:
Background in Specman.
Knowledge in HDL (Verilog/VHDL).
Knowledge in Mixed Signals, Analog, and Behavioral Models for Verification.
Knowledge in Chip boot and Infrastructures.
This position is open to all candidates.
 
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
21/06/2026
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for an experienced Design Engineer to join the YU design team and develop the next generation technologies.

As a design engineer in the YU design team, you will participate in definition and implementation of our boot and chiplet control technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.

What you'll be doing:
In this position, you will be responsible for defining, coding and integrating sophisticated boot components into various projects and using state-of-the-art technologies.
As a member of our YU design team, you will participate in defining various boot and chip controller features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.
Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.
Requirements:
What we need to see:
B.SC./ M.SC. in Computer Engineering/Electrical. Engineering/Communication Engineering.
5+ years of practical experience.
Exposure to rtl implementation and coding.
Familiarity with verification tools.
Strong debugging, problem solving and analytical skills.
Strong communication and social skills are required.
Ability to work in a geographically diverse team environment.
Self motivated, independent and target oriented.
High Level of English.

Ways to stand out from the crowd:
Prior Design or Verification experience.
Experience in developing sophisticated design blocks.
Knowledge in Mixed Signals, Analog, and Behavioral Models for Verification.
Knowledge in Chip boot and Infrastructures.
Experience in working with back-end on area, power and timing closures.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8703701
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
21/06/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for an excellent Senior Firmware Engineer to join the Firmware team. The Firmware team develops groundbreaking networking features for AI, cloud, HPC and storage. We drive the data growth of the worlds biggest companies. With many hardworking engineers around the globe, the work environment is complex, results-oriented and fast paced. You will learn how a big software project is operated, maintained, qualified and released, and how Hardware and Firmware are developed

What you will be doing:

Work closely with the architecture and different software and hardware design teams.

Implement new features for our NIC and Switch firmware.

Develop verification tests for advanced features in a highly complex and sophisticated Firmware testing environment.

Collaborate with multi-functional teams including chip design, board designers, Silicon, SW and program managers to debug any FW/validation issues.

Heavily involved with the early modeling and simulation required to produce our outstanding products including schematic and layout reviews on next generation board designs.
Requirements:
What we need to see:

Bachelor's or master's Degree in Electrical/Computer Engineering, or equivalent experience are required.

Prior 8+ years of experience in Firmware.

Strong C/C++ and OOP capabilities.

Excellent Data analysis, debugging and problem-solving skills.

Strong understanding of digital design, computer architecture, Linux, drivers and CPU/GPU/SOC architecture.

Familiar with the fundamentals of Linux scripting languages and python hands-on.

Strong analytical, debugging and problem solving skills.

Motivated and independent with strong communication skills.


Ways to stand out from the crowd:

Familiarity with FIPS certification process and crypto engines.

Coding and automation skills in scripting languages like Python.

Experience with RISCV architecture and verification.

Ability to multitask and prioritize in a fast paced environment.

Strong interpersonal and communication skills and ability to work effectively across different teams.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8703700
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סגור
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
21/06/2026
Location: Yokne`am
Job Type: Full Time
We are looking for a Chip Design Manager to join our Networking team! As a Chip Design Manager in our Networking Business Unit, you will lead a team of highly skilled engineers responsible for verifying the next generation of our cutting-edge network products and GPU technologies. This is a unique opportunity to make a real impact at the heart of our AI and HPC revolution, while working in a fast-paced, innovative environment. You will join a passionate, experienced team working at the forefront of silicon verification - using advanced methodologies and tools to ensure design correctness for world-class solutions in data centers, high-performance computing, networking, and storage.

What You'll Be Doing:

Lead and grow a team of formal verification engineers focused on pre-silicon FV of complex digital designs.

Define and drive strategies and methodologies across multiple projects to prove design correctness and ensure quality.

Collaborate closely with Architecture, Design, and DV teams to identify verification needs and drive closure.

Provide technical guidance, mentoring, and support to engineers on the team.

Own planning and execution of verification deliverables to ensure high quality and timely tapeouts.
Requirements:
What We Need to See:

BSc or MSc in Electrical/Computer Engineering, Computer Science, or Mathematics.

5+ years of managerial experience leading engineering teams in chip design or verification.

8+ years of industry experience in RTL design, functional verification, or related domains.

Strong understanding of chip design flows and verification methodologies.

Excellent leadership, analytical, problem-solving, and communication skills.


Ways to Stand Out from the Crowd:

Experience with formal verification tools and methodologies (e.g., JasperGold, VC Formal).

Background in assertions, coverage models, or formal testbench development.

Track record of building and scaling high-performing engineering teams.

A passion for recruiting, mentoring, and developing talent.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8703690
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דיווח על תוכן לא הולם או מפלה
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שליחה
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v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
21/06/2026
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for an experienced DFT Design Engineer to join the DFT design team and develop the next generation DFT technologies.

As a design engineer in the DFT design team, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.

What you'll be doing:

In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.

As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.

Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.
Requirements:
What we need to see:

B.Sc. in Electrical Engineering or Computer engineering or equivalent experience.

5+ years of practical experience.

Exposure to rtl implementation and coding.

Familiarity with verification tools.

Strong debugging, problem solving and analytical skills.

Strong communication and social skills are required.

Ability to work in a geographically diverse team environment.

Self motivated, independent and target oriented.


Ways to stand out from the crowd:

Prior Design or Verification experience.

Experience in developing sophisticated design blocks.

Integration of design elements to large cluster or full-chip.

Experience in working with back-end on area, power and timing closures.

Scripting ability.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8703659
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