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Lead hands-on lab debugging to fix complex silicon performance, characterization, and yield issues. Use bench findings and board-probing data to give feedback directly to the architecture and design teams. Lead ASIC bring-up on validation boards, focusing heavily on SerDes, high-speed interfaces, and power/clock domains. Run characterization across PVT (Process, Voltage, Temperature) conditions and analyse large datasets to resolve performance bottlenecks and improve chip yield. Write and optimize clean Python code to automate lab equipment and test internal chip logic. Serve as the technical lead for complex hardware debug, defining validation methodologies, and advanced lab measurement techniques for the team.

We are transforming the industry and building a new internet for the 5G era, providing a unified, programmable silicon architecture that is the foundation of all future routing products.

Our devices are designed to be universally adaptable across service providers and web-scale markets, designed for fixed and modular platforms. Our devices deliver high speed without sacrificing programmability, buffering, power efficiency, scale or feature flexibility.

Cisco Silicon One is a revolutionary, ground-breaking technology for our customers and end users for decades to come! The Internet now has a new faster, better, safer engine!

Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.

Key responsibilities include:

Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.

What Youll Do:

Our unique design center integrates all silicon hardware and software development disciplines under one roof. We are revolutionizing the industry by building a new internet for the 5G era, with a unified, programmable silicon architecture that will underpin future routing products. Our devices are designed for adaptability across service providers and web-scale markets, delivering high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility.

We are looking for an excellent Senior System Validation Engineer!
Our Networking division is a leading supplier of innovative end-to-end InfiniBand and Ethernet connectivity solutions and services for servers and storage. We offer market-leading solutions that include adapter cards, switches, cables, and software to support networking technologies. Our products optimize data center performance and deliver industry-leading bandwidth and scalability. In addition, we serve a wide range of markets including high-performance computing, enterprise, data centers, cloud computing, big data, and Web 2.0. We are constantly reinventing ourselves to stay ahead of the market and bring groundbreaking products and services to the industry.

What you'll be doing:

Test Verification and Validation (both HW and SW).

Maintain products quality by improving test stability, coverage, design, and manufacturing process in Mass Production.

Execute tests in different scopes such: as regression, performance degradation, functional, and security; report the progress of testing and provide summary reports of the activity.

Troubleshooting and streamlining/optimizing our testing procedures.

Support Mass production matters.

Debugging production bugs and solving them.

Our Networking division is looking for an excellent System Validation Engineer! Our Networking division is a leading supplier of innovative end-to-end InfiniBand and Ethernet connectivity solutions and services for servers and storage. We offer market-leading solutions that include adapter cards, switches, cables, and software to support networking technologies. Our products optimize data center performance and deliver industry-leading bandwidth and scalability. In addition, we serve a wide range of markets including high-performance computing, enterprise, data centers, cloud computing, big data, and Web 2.0. We are constantly reinventing ourselves to stay ahead of the market and bring groundbreaking products and services to the industry.

What you'll be doing:
Test Verification and Validation (both HW and SW).
Maintain products quality by improving test stability, coverage, design, and manufacturing process.
Execute tests in different scopes such: regression, performance degradation, functional, and security; report the progress of testing and provide summary reports of the activity.
Troubleshooting and streamlining/optimizing our testing procedures.
Support production matters.

We are looking for best-in-class STA (Static Timing analysis) Physical Design Engineers to join our outstanding Networking DFT team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:
DFT STA execution, from rtl driven constraints and definitions through DFT constraints quality assurance to STA sign-off.
Be part of a unique team of experts who have deep understanding in all aspects of pre and post silicon.
Be exposed and work on a variety of challenging designs, unique DFT solutions that require deep silicon implementation understanding.
Daily work involves all aspects of static timing analysis - constraints, environment, models generation and timing ECO generation for block level and full chip level.
Taking part in flows development.

We are looking for an outstanding Manager, Infrastructure Engineering - Networking to lead a high-impact infrastructure engineering team. The team develops and maintains engineering infrastructure solutions that enable R&D teams to provision, validate, test, debug, and recover complex server and networking environments at scale.

In this role, you will lead a team that provides infrastructure platforms and hands-on engineering support for internal customers across firmware, driver, hardware, software, and verification organizations. The position combines deep technical leadership with people management, execution ownership, customer support, and operational excellence in a fast-paced R&D environment. We are looking for a strong technical manager who can grow and mentor engineers, set technical direction, drive recovery of complex systems, optimize customer flows, and deliver reliable infrastructure capabilities in our scale.

What youll be doing:

Lead and grow an infrastructure engineering team responsible for bare-metal provisioning, VM infrastructure, server fleet automation, CI/CD infrastructure, customer-facing debug support, and high-performance networking environments.

Own the teams technical roadmap, priorities, execution plans, and delivery commitments across multiple infrastructure initiatives, while balancing long-term platform improvements with day-to-day customer needs.

Drive ownership of VM box inventory and lifecycle management across many Linux distributions, including image readiness, OS compatibility, package baselines, kernel configurations, provisioning flows, and production availability.

Build infrastructure capabilities that enable engineering and verification teams to run provisioning, testing, validation, and debug workflows efficiently and reliably, without positioning the team as the owner of verification itself.

Lead customer support, debug, and optimization of internal customer flows, including triage, root-cause analysis, bottleneck removal, workflow improvements, and clear communication with engineering stakeholders.

Guide complex system debug and recovery in a firmware R&D environment, including server bring-up issues, driver and firmware interactions, boot failures, networking problems, lab instability, automation failures, and environment recovery.

Provide technical leadership for Linux-based automation platforms, including server lifecycle management, OS installation, kernel configuration, driver setup, inventory management, resource allocation, observability, and production readiness.

Partner closely with firmware, driver, hardware, software, cloud, and verification teams to define requirements, improve reliability, and deliver infrastructure solutions that accelerate engineering productivity.

We are now looking for a Senior Chip Design Verification Engineer for the Switch Silicon group.

As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:
Work in a combined design and verification team which develops some of the switch silicon core units.
Build reference models, verify and simulate chip blocks/entities according to specifications.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.

We are looking for a Senior Chip Design Engineer to join our Network Adapter Silicon group. As a Senior Design Engineer in our Networking Silicon team, you will join a group of passionate engineers to design and implement the next generation state-of-the-art Networking Silicon chips. In this position, you will make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a combined design and verification team which develops core units within the Networking silicon.

Own micro-architecture definition and RTL implementation of chip blocks/entities according to specifications, performance, timing, area and power requirements.

Drive your design through the full implementation flow - synthesis, timing closure, lint/CDC and physical design constraints - together with the backend teams.

Work closely with multiple teams within organizations such as Architecture, Micro-Architecture, Verification, FW and Post-Silicon validation.

We are looking for a Technical Support Engineer dedicated to supporting Slurm for our customers. You will join a dedicated team of Slurm subject-matter guides, owning sophisticated support cases and helping customers run reliable, efficient, and highly scalable clusters. This role requires extensive production experience with Slurm and the ability to diagnose issues across the scheduler and the surrounding Linux, networking, storage, authentication, database, and GPU infrastructure.

What you'll be doing:

Own Slurm support cases from initial investigation through resolution for customers running production AI and HPC clusters.

Diagnose complex problems involving slurmctld, slurmd, slurmdbd, job scheduling, node management, resource allocation, accounting, authentication, and high availability.

Solve Slurm configuration and policy features, including partitions, reservations, priorities, fair-share, quality of service, backfill, preemption, GRES/TRES, cgroups, and job constraints.

Investigate performance, reliability, and scalability issues using logs, diagnostic data, configuration analysis, reproductions, and source-level debugging when required.

Isolate problems across Slurm and its surrounding dependencies, including Linux, MUNGE, databases, networking, parallel storage, containers, GPUs, and cluster-management systems.

Advise customers on Slurm configuration, upgrades, operational practices, managing system resources, and safe recovery from production incidents.

collaborate with engineering teams by producing clear technical descriptions, reproducible test cases, and well-supported defect reports.

Develop guides, knowledge-base articles, diagnostic tools, and internal training that strengthen Slurm expertise across the support organization.

We are looking for a passionate and talented SW & System Architect to join our SW Architecture group. The position includes researching new technologies with focus on architecture definition of groundbreaking technologies in different domains - networking, security, virtualization and orchestration. Our Architecture group consists of world-class architects responsible for designing the next generation state-of-the-art architecture for our DPUs & NICs technologies.

You will play a key role defining the future of cloud solution stack, from HW to Application level, including orchestration, provisioning, network programmability and SDN. You will be working with various teams around the world including SW architects, R&D, product, solution architects and external customers. This position offers a unique and exceptional opportunity to have real impact in a dynamic, technology-focused company shaping the future of data-centers technologies.

What you will be doing:

Lead architecture for cloud-networking including orchestration, provisioning and security solutions.

Design state-of-the-art system architecture for DPUs & NICs technologies.

Build end-to-end solutions from application level to HW.

Responsible for writing effective, clear and reliable architecture specification.

Evaluate new technologies and innovate & rapidly develop POC prototypes that can then be developed into full-fledged products/solutions.

Work closely with different teams around the world including sw & hw architects, R&D, product, solution architects, application and field engineers and more.

Work with high profile customers on advanced and future technologies and solutions.

Our Network Modeling and Performance Insights group is seeking a skilled and driven senior software engineer for the design and development of our internal advanced AI-networking simulation service. The simulation service is a critical tool for developing and improving our AI system offering and has direct influence on HW and SW design, network architecture, performance characterization and optimization.

In this role, you will be responsible for developing and optimizing the network simulation service. You will enhance the simulator performance and quality and scale it to support massive loads, additional clients and unique use cases. You will work on integrating this infrastructure with cloud computation services and ensure the simulation is available as a service for AI agents and internal customers. If you're passionate about tackling intricate challenges and contributing to comprehensive software solutions, we want to hear from you.

 

What you'll be doing:

Design and develop simulation capabilities, integrating internal and external libraries and maintaining a clean, scalable architecture for a complex SW project.

Expand the simulation versatility to accommodate advanced use cases and bleeding-edge requirements. Provide innovative solutions to scalability and fidelity trade offs of the simulator.

Improve the quality of the simulation as a software product, ensuring robustness and reliability.

Expose the simulation as a service to facilitate easier access for different stakeholders.

Enhance simulation runtime and memory consumption through creative optimization techniques.

Integrate a new simulation management system, making simulated experiments data accessible to all users.

Collaborate with DevOps engineers to develop our CI/CD infrastructure for the networking simulation service, ensuring efficient deployment and smooth integration processes.

The Networking Application Engineering team is looking for a motivated, experienced Senior Hardware Engineer who thrives at the intersection of hardware performance, ecosystem validation, and ODM/OEM partnerships. In this high-impact role, you will own critical qualification tooling, drive the design-in process with leading hardware partners, and collaborate across םור R&D organization to accelerate hardware resolutions at scale. Your work will directly influence the quality and velocity of next-generation networking hardware reaching the world's most advanced data centers and supercomputers.

What You'll Be Doing:

Own and lead the Hardware Performance and Qualification tooling suite, driving continuous improvement in test coverage, automation, and accuracy in collaboration with leading ODMs and OEMs.

Drive the design-in process with top-tier ODM and OEM partners, ensuring seamless hardware integration and delivering best-in-class platform experiences.

Partner cross-functionally with multiple R&D departments to identify, escalate, and resolve hardware issues rapidly - reducing time-to-resolution and maintaining platform quality.

Define and execute qualification plans for new hardware platforms, validating performance, stability, and compliance across diverse system configurations.

Build and nurture trusted technical relationships with ODM/OEM engineering teams, acting as the go-to expert for hardware performance and qualification.

Provide actionable feedback to engineering and product teams based on qualification findings and partner interactions.

We are seeking best-in-class ASIC Design Engineers to design and implement the worlds leading CPU's and SoC's. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We are a learning machine that constantly evolves by adapting to new opportunities that are hard to pursue, that only we can take on, and that matter to the world. We have crafted a team of excellent people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.

We are building a new group in Israel, this group will deliver security engines and risc-V processor IPs to all of our product lines working with all our groups around the world. We are looking for an Architect with a security experience to help lead the Arch work on security engines and secure boot flows. You will work closely with our security architects, design engineers, verification engineers, and SW engineers to accomplish your tasks.

What you will be doing:

Participate in Architecture development and document specifications.

Work with RTL and the verification team to ensure that the design meets the spec.

Help deliver a design that meets the high security standards of us and our customers.

Our Switch ASIC group is seeking a top-tier ASIC technical manager to lead the development of our next-generation ASICs. Join us in shaping the future of technology! As an ASIC Project Lead, you will manage the pre-silicon development of NVIDIA's most advanced and complex switch ASICs - from concept to tape-out - and drive the chip through power-on and qualification to production release. You will collaborate with a cross-disciplinary team, interacting with unit-level ASIC, Physical Design, CAD, Package Design, Firmware & Software, DFT, System Design, Analog Design, and other specialized teams.


What you'll be doing:
Development Management: Lead the ASIC development from concept and architecture stages through micro-architecture, design, verification, and physical design until tape-out.
Post-Silicon Execution: Drive chip power-on, bring-up, and qualification to production release.
Execution Plans: Define and implement execution plans in collaboration with cross-discipline leaders in unit-level, full-chip, physical design, and firmware/software emulation.
Roadmap Definition: Contribute to the definition of NVIDIA's switch ASIC roadmap.