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Required Integration and Validation Architect
About the team:
Join our hardware systems team to drive DV/PV software readiness for our AV-HW Tier 1 products. Youll combine customer-facing technical leadership, detailed validation design and hands-on integration to secure internal acceptance and customer satisfaction with testability and coverage.
What will your job look like:
Youll lead customer technical reviews, present readiness and validation evidence, and resolve concerns about testability and coverage.
Youll translate customer expectations and system requirements into detailed integration plans, coverage, loads, diagnostics and monitoring requirements.
Youll define interfaces between DV/PV software, SoCs, test hosts, equipment and automation, guiding teams and suppliers through implementation and verification.
Youll bring up test setups, integrate hardware and software releases, and troubleshoot issues using measurements, logs and controlled experiments.
Youll use technical judgment to coordinate investigations and corrective actions across teams, and verify that issues are resolved.
Youll own technical documentation and customer review material, keeping coverage tables, procedures and reports aligned with demonstrated capabilities.
Youll accept or withhold technical readiness against agreed requirements and assess the validation impact of hardware and software changes.

Our Unit Level Verification Team in Haifa is looking for an experienced verification engineer to be involved in the development of our future AI and deep learning HW accelerators.
This is an exciting opportunity to join a team of highly talented engineers, working on the most cutting-edge technologies to deliver our EyeQ future chips, aimed to power the worlds first fully Autonomous Vehicle!
What will your job look like:
Define, implement and enhance verification environments using UVM methodology.
Write and debug tests that combine UVM methodology and SW code.
Identify and write various types of coverage measures.
Collaborate with designers, architects, and SW developers from Haifa and Jerusalem teams to deliver the most comprehensive verification environment.
Integrate Industry Standard (such as AXI and OCP) and other 3rd party VIPs.

Required Experienced SoC Verification Engineer
About the team:
Our SOC verification group owns the important and challenging job of verifying our chip. It is involved from product specification to final SOC delivery, and involves all the system components. The group is made up of few of the best verification engineers, so besides contributing to making our roads safer, youll get the chance to work at one of the most professional verification teams.
What will your job look like:
You'll be responsible for Pre-Silicon system-level verification of the most cutting-edge AI accelerators and technologies in the automotive field.
Define the TestPlan, develop and run tests on simulation/emulation environments, develop test environment and verification collaterals.
You'll have a broad effect on our unique product from the very beginning of the process.

Were looking for an Experienced Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner, leading the process from RTL to GDS.
Lead floorplan exploration in collaboration with Front-End and Architecture teams.
STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis.
Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks.
Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area).
Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

The Automated Driving Hardware group in Haifa is looking for an Experienced Formal Verification Engineer to join a team of talented engineers developing next-generation silicon for autonomous driving platforms.
This is a unique opportunity to enter one of the most challenging and rewarding disciplines in hardware development. Formal Verification combines deep understanding of computer architecture, digital design, and advanced verification methodologies to prove hardware correctness and uncover bugs that traditional testing may never find.
What will your job look like:
Be the owner of formal verification environment from first draft to sign-off stage.
Apply formal methods to verify the correctness of various complex digital systems.
Work with HW architects\designers to define assumptions, rules and cover properties.
Help define the formal verification methodology and environment to be applied by the team.
Explore new Formal methods and Tools.
Work with tools like Cadence JasperGold, Verisium manager, Xcelium, Indago.
Analyze verification results, identify bugs, and collaborate with engineers to resolve design issues.
Develop generic formal blocks\functions of commonly used logic, to be later used off the shelf.

Our Automated Driving group is looking for an experienced DFT Engineer.
This is an exciting opportunity to join a team of highly talented engineers, working on one of the most cutting-edge technologies - Autonomous Vehicle (AV) SoC.
At our Automated Driving group, we know that the idea of a fully autonomous car is no longer science fiction, but a reality that we are creating!
We have spent more than 15 years developing the world's most Advanced Driver Assistance Systems (ADAS) and we are now leading the computer vision and machine learning domain, reaching fully automated driving experience (AV).
What will your job look like:
Develop all the necessary HW / FW / SW for the different modules.
Verify and Validate our design.
Debug and analyze coverage and yield loss.
As a cutting edge technology company, we are working only with the very advanced DFT tools and features, while developing our own methods and DFT concepts - as it required by the Automotive and Safety related products market (ISO26262).

Required Experienced Deep Learning Optimization Engineer- Compilers Team
About the team:
We are the world leader in automotive and driving assistance systems, developing the world's most advanced software technologies and hardware architectures.
We are providing an end-to-end software solution for development and deploying features on its HW chip - EyeQ.
The compilers team is looking for a C++ Software engineer with a passion for low level optimizations and code analysis.
What will your job look like?
Develop and extend a compiler based on the LLVM infrastructure to support and optimize our EyeQ hardware.
Implement and improve middle‑end and back‑end compiler optimizations.
Analyze generated code to improve performance and efficiency.
Perform real-world benchmark analysis to find optimization opportunities.
Collaborate with chip architects on defining and supporting future hardware generations.

Our Autonomous Driving software group is looking for an OS expert with strong knowledge in the Linux Kernel. As a Linux Operating System architect, you will be responsible to work with system and SW architecture teams to define OS solutions to satisfy customer requirements for the autonomous vehicle world. This involves security and connectivity components in our Safety critical Linux OS involving both the Kernel and the user space worlds.
This is an exciting and unique opportunity to work with highly talented Linux OS team and be a leader in the development of the Linux as a platform for the Safety Critical Automotive industry.
What will your job look like:
Defining and designing OS solutions for the security and high-speed connectivity requirements.
Conducting PoC activities to verify architectural decisions and resource allocation involving SW Simulators.
Writing architectural design specification documents, defining KPIs and testing criteria.
Working with the development teams closely to review design and test plan documents.
Performing performance analysis to maximize performance and optimize HW utilization while maintaining the real time behavior.

Our Autonomous Driving group in Haifa is looking for an Electrical Validation & Embedded SW Engineer. This is an exciting opportunity to join a growing team of highly talented engineers, working on the worlds most advanced SoCs for ADAS and self-driving vehicles.
Electrical Validation engineers enable, debug, and validate high-speed interfaces - like LPDDR4/5/6, PCIe Gen4/5, CDPHY, and MPHY - using high-end Lab measurement equipment and advanced SW tools. This dynamic work environment requires interfacing with Silicon and hardware design engineers, Software developers, Signal Integrity, and System Validation teams. The proximity to Signal/Power integrity simulation activities - we are a single SIPI/EV team - is another powerful advantage, enabling joint simulation-measurement effort.
What will your job look like:
You will join a team of talented and experienced EV/SI/PI engineers with wide scope of responsibility, from Pre-Si SI/PI simulations to Post-Si Electrical validation and debug, covering all the high-speed analog interfaces of our EyeQ products.
Responsibilities include performing electrical spec compliance and system margin validation, interface optimization, statistical results analysis, validation flow definitions and automation, validation SW tools development, etc.
You will also deal with FW development, automation enabling, data post-processing and debug of high-speed interfaces, like LPDDR4/5, PCIe Gen4/5, and D/C/MPHY.

Required C++ Software Engineer - Tools Team
About the team:
What will your job look like:
You will lead and develop various development tools, technologies and SW infrastructures for our platform including simulators, data analysis, debugging tools and performance optimization tools.
You will get a deep understanding of our HW architecture as well as end-to-end use cases and CV\DL algorithms.
You will work on different environments in our software stack including backend, middleware and frontend development.
You will consistently work and interact with multiple departments.
You will have a great chance to influence future generations of our hardware and software stacks.

Required ASIC Design CAD Engineer
About the team:
We are looking for a talented energetic customer-obsessed team player, with knowledge of Logic design environment, scripting experience, and strong self-motivation to develop Tools and Scripts and perform Logic Design flows as part of an ASIC Design CAD Engineer role developing next-generation autonomous vehicles EYQ chips.
What will your job look like:
Develop and implement design automation tools and scripts.
Perform logic design flows from high-level design to synthesis and power analysis.
Evaluate and explore new automation technologies and advocate for efficiency improvements.
Evaluate multiple vendor solutions and guide execution, in the most optimal use, based on design needs.
Effectively communicate and support large number of design engineers, providing high-quality tools and flows, documentation, and presentations.

We are looking for an Algorithm Developer who will be challenged to solve real-world problems using Computer Vision and Signal Processing techniques. Our mission in the Algorithms department has a significant impact on autonomous driving technologies and on saving lives.
In this position, you will combine classic programming and algorithm development in Python and C++, and be responsible for maintaining the product and developing new features. As an Algorithm Developer, you will learn and develop new algorithms that can address new problems and challenges as they arise.
The work in our algorithms department is dynamic and involves developing algorithms from the early stages of research through to production, while collaborating with other teams throughout the organization.
What will your job look like:
Your job will include a combination of classic programming and algorithm development.
You will develop in both C++ and Python.
You will need to both maintain the product and develop new features.
You will need to learn and develop new algorithms that can address new problems as they arise.

As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of Full chip, IP, and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.