לוח משרות דרושים מהנדס אלקטרוניקה

This role has been designed as Hybrid with an expectation that you will work on average 2 days per week from our office.

Roles and Responsibilities:
Design, develop, and enhance I/O subsystems, virtualization, kernel programming, and memory management for cutting-edge system software products.
Drive performance optimization, and efficient memory management.
Perform in-depth debugging, triaging, and resolution of user and kernel-level, performance profiling, and memory-related issues.
Develop innovative solutions, addressing challenges in virtualization, multithreading, and hardware-software interaction.
Explore and implement new methodologies fostering continuous improvement and innovation.
Proactively identify bottlenecks in system design, and recommend and implement robust, scalable solutions.
Stay updated on evolving trends in kernel development, design, and virtualization technologies to bring innovative practices to the team.
Troubleshoot and optimize complex I/O and kernel features to enhance performance, scalability, and reliability.
Collaborate with cross-functional teams to align on design goals and ensure seamless integration with the system architecture.
Exhibit flexibility in taking on new or related tasks, showcasing adaptability and a proactive, problem-solving mindset.
Provide technical leadership in architecture design, problem-solving, and decision-making across complex technical domains.
Lead technical discussions, design reviews, and decisions on critical system challenges, driving the adoption of innovative solutions and best practices.

We are currently seeking an Application Engineer for our European Technical Organization, with focus on the Calibre line of products, market leader in physical verification and circuit verification.
The primary purpose of the position is to work closely with customers, and sales team to manage the technical engagement that supports sales campaigns and drive the adoption of our company Calibre software tools.
Responsibilities -
To develop close relationships with customers to be able to assess their technical requirements and the options/ability for our company's Calibre solutions to develop and implement technical sales plans. This may be through proactive telephone contact, delivery of presentations and demonstrations, articulating product value statements, and engagement in technical benchmarks and evaluations.
To drive products into customer projects to ensure adoption by creating methodology and flows; this may include infrastructure and integration into a customers environment and the identification of pilot projects for tool use and the debugging and bring-up of new methodologies and flows.
To uncover or qualify new opportunities, the technical viability of a lead and communicate the opportunity clearly to the sales team. Use this information to establish success criteria for technical engagements that effectively position our company areas of strength.
To provide technical leadership on all aspects of a sales campaign with the aim of contributing to account/area technical business plans.
To share, in a proactive manner, account, evaluation, competitor, technology and other useful information with peers, sales teams, management and product divisions to help us to compete more effectively.
To actively participate in out-bound marketing such as trade shows, workshops, seminars, webcasts.
We are seeking a highly motivated,results oriented and accountable person that strives on working in an international environment.
The position is based in Israel although you will be part of a team covering Europe and consequently should anticipate some international travel in Europe and US.

we are looking for an experienced Embedded software engineer to join our software team. Youll be the single owner of the software stack on one of our satellite programs - ground station through flight computer to payloads. The code, the builds, the CI, and the system integration are yours. Youll work alongside hardware engineers during system bring-up and the wider software team day-to-day. Were looking for someone who reads documentation and ships independently.
Responsibilities:

* Own the software stack across ground station, flight computer, and payloads
* Maintain Yocto-based payload software: build, package, deploy
* Write and maintain the Embedded and host-side software
*  Integrate code contributions from adjacent teams and turn them into shippable software
* Partner with hardware engineers on system bring-up and integration
* Debug across hardware, Kernel, and userspace
*  Write and maintain automated tests and technical documentation
Advantages:

* Background in defense or other Embedded - system -of-systems environments
* Experience with constrained or resource-limited Linux platforms
* Docker / containerization experience
* Familiarity with Embedded interconnect protocols (I2C, SPI, UART, RS422/485) and integrating drivers that use them

we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Physical Implementation & Execution

Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity

Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration

Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust

we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Physical Implementation & Execution

Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
Own macro-level implementation with deep hands-on experience in floorplanning and complex routing
Signoff & Design Integrity

Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
Ensure first-pass silicon success through rigorous signoff flows and analysis
Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness
Methodology Development & Cross-Functional Collaboration

Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
Leverage scripting and automation to make engineering environment faster and more robust

we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.

As a Senior ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Design Ownership & Implementation

Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams
Quality Assurance & Design Optimization

Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities
Methodology Innovation & Collaboration

Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration

we're seeking a visionary Senior DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.

As a Senior DFT Engineer, you will be at the intersection of architecture, design, and production. You won't just run tools-you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable. If you thrive on solving complex challenges in deep-submicron processes and want to establish world-class DFT methodologies, this is your opportunity.

Key Responsibilities

DFT Architecture & Strategy

Own the DFT journey from high-level architecture definition and RTL design to backend implementation and post-production support
Develop comprehensive Design-for-Testability (DFT) strategies for next-generation connectivity platforms, ensuring chips meet the highest quality standards
Define DFT architectures including JTAG/iJTAG, MBIST, Scan, and ATPG methodologies
Test Pattern Development & Optimization

Generate and optimize high-quality test and debug patterns for production
Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations to ensure robust performance
Drive test coverage and quality metrics to meet stringent manufacturing requirements
Cross-Functional Collaboration & Methodology Innovation

Act as a multidisciplinary bridge, collaborating closely with Architecture, Verification, and Backend teams to ensure seamless integration and optimal QoR
Participate in developing and maintaining cutting-edge DFT implementation flows
Automate and improve methodologies using advanced scripting and tools

we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the worlds largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities


Execute SoC Top-level physical design and actively drive full-chip convergence
Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration

we're seeking a highly skilled Front-End CAD Engineer to join our local engineering powerhouse from the ground up.

As a Front-End CAD Engineer, you will be the backbone of our chip design ecosystem. You wont just be using tools; youll be architecting the methodologies, automation scripts, and design flows that enable our hardware teams to push the limits of silicon performance. Your work directly impacts the productivity of the design team and the time-to-market for our next-generation processors.


Key Responsibilities

Develop, maintain, and optimize RTL generation tools, building automated IPs and SoC schemes
Create robust applications using Python and Tcl to automate models build, regression and analysis tools and other assisting tools for all disciplines in front-end flows
Evaluate and integrate Electronic Design Automation (EDA) tools from vendors like Cadence, Synopsys, and Mentor Graphics
Define the methodologies of usage and integrate AI tools in this fast-growing field impacting all VLSI development flows

we're seeking a visionary Package Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, Driving the physical implementation strategy for chips that power the world's largest AI clusters.

As a Package Design Engineer, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon. You will execute the package flow, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners. You will be responsible for implementing package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling products to operate reliably in the worlds most demanding AI and cloud environments.

Key Responsibilities


Execute end-to-end IC package design, from early feasibility and detailed design through to qualification and high-volume manufacturing
Implement package architecture and utilize advanced technologies (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
Drive signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
Perform package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and apply mechanical constraints
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
Interface directly with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets are met
Conduct package-related risk assessments, failure analysis, and corrective actions during bring-up and production ramp
Support NPI, qualification, and product sustainment activities, including vendor technical reviews

we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Extraction to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.

Key Responsibilities

Develop, qualify, and maintain automated RC extraction flows for high-performance AI SoCs
Own the setup and validation of foundry technology files (e.g., StarRC/Quantus techfiles, TLU+, ITF) across various process corners
Perform correlation studies between different extraction tools and 3D field solvers (e.g., Raphael, QuickCap) to ensure modeling accuracy
Collaborate closely with the Signal Integrity (SI) and Power Integrity (PI) teams to provide accurate parasitic data for critical high-speed nets and power grids
Implement automated scripts (Tcl/Python) to streamline extraction regressions, data parsing, and PEX-to-STA (Static Timing Analysis) handoffs
Analyze the impact of layout effects (LDE) and parasitics on timing and power, providing feedback to the implementation team to optimize PPA
Interface with EDA vendors and foundries to resolve extraction tool bugs and methodology gaps related to advanced nodes (5nm/3nm)

we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities


Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient

Are you looking for a great opportunity to further your career? we are investing in the rapid growth area of Hardware Assisted Verification (HAV).
Our most successful multi-national customers are using our company HAV platforms to verify some of the worlds most advanced System on Chip (SoC) designs. HAV solutions are expanding to a wider audience of smaller companies who are benefiting from early software development and ultra-fast hardware verification through hosted services.
we are looking to hire a Senior Consultant with either Emulation or FPGA prototyping knowledge and experience. This role is ideally suited to someone with a good understanding of HAV platforms who can guide customers through successful HAV deployment and design validation. This is a great opportunity to work with some of the most interesting and innovative people and companies across the semiconductor industry.
The consultant role will be mainly focused on technical services delivery. This could range from platform enablement to methodology guidance. Interactions may be direct with the customer or collaborative through a wider technical team. This position will require a combination of remote, office and onsite working. As a consultant, you will also be expected to uncover opportunities, scope engagements, promote offerings, and grow new business.
Key Responsibilities
A good understanding of HAV platforms and infrastructure (e.g. Strato, Primo or proFPGA enterprise-level systems would be preferable)
A good understanding of HAV compilation and runtime flows (e.g. Veloce or VPS would be preferable)
Practical insights into the application and usage of HAV
Knowledge of design mapping, testbench mapping and pre-silicon validation
Familiarity with HAV debug solutions (probes, waveforms, assertions, coverage, etc.)
Knowledge of virtual TestBench eXpress (TBX) and/or In-Circuit Emulation (ICE) use-cases
Proficient in HDLs (Verilog/SV) for RTL design and HVLs (SV/UVM) for verification
Strong background in functional verification, RTL synthesis, design partitioning and place-and-route
Conversant with SoC design and architecture concepts.