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Required Physical Design Team Leader
Description
We are reimagining high-performance computing (HPC & AI). Our accelerated compute solutions leverage intelligent adaptive algorithms to vastly accelerate supercomputers, driving them forward into a new generation. We have developed a novel software-defined hardware architecture that is achieving significant advancements in both the HPC and AI domains.
Everything we do is guided by three core values:
Professionalism: We strive for exceptional results through professionalism and unwavering dedication to quality and performance.
Unity: Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard.
Impact: We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide.
Come help lead the design and development of one of the most ambitious products at the forefront of compute technology!
Responsibilities
Lead a physical design team responsible for all stages of the physical design process-floor planning, placement, clock tree synthesis, routing, timing, and power optimization at both block and subsystem levels.
Mentor and guide a team of physical design engineers through all stages of the design flow.
Collaborate closely with project managers and other technical leads to ensure timely delivery and successful completion of projects.
Drive the technical direction of the physical design process to ensure efficient, high-quality outcomes.
Develop and implement best practices for physical design and continuous improvements of design workflows.
Optimize designs for performance, power, and area (PPA) to meet project goals.
Ensure compliance with DRC (design rule checking) and LVS (layout versus schematic) requirements. .
Drive timing analysis and closure, working closely with the RTL design team to resolve timing violations.

We are looking for a talented and experienced Physical Design lead to take part in the physical design and help lead the companys BE activities . This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on our final product
Responsibilities:
Lead blocks and sub systems execution from RTL to GDSII.
Clearly reflect status and execution metrics and help identify and solve execution bottlenecks.
Spec and define full floor plan, including pin placement, partitions, and power grid
Develop and validate high-performance, low-power clock network guidelines
Perform critical block-level place and route and create designs that meet PPA targets.
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations
Work with vendors on defining physical design methodologies and assist in flow development for chip.

We are looking for a talented and experienced engineer to take part in the Emulation and Prototyping efforts for the companys core product.
This position involves building a complex emulation environment from scratch, and collaborating with software, design, and verification teams. In this role, you will be leading emulation from A to Z and will have a critical impact on the company.
Responsibilities
Develop and build complex emulation models for coming generations of our accelerators, including transactors like PCIe, SPI, and embedded CPUs
Work with the software, design, development, and verification teams to understand the functional and performance goals of the products design
Optimize the model for speed and capacity and develop debug abilities to support software and firmware teams
Work with software design and development teams to define and develop BFM, test bench, and checker tools
Review specifications and develop attributes, tests, and coverage plans for the emulation system.

We are seeking an exceptional architect to join our architecture team and shape the future of quantum control. We have a unique opportunity to set the architecture of the next-generation quantum computers towards utility scale quantum computing.
In this role, you will lead the architecture definition of the next generation quantum control system, from units/building blocks roles and responsibilities, core components such as DACs/ADCs, FPGAs, communication interfaces and power and cooling solutions .Designing a scalable architecture of quantum control requires deep understanding of quantum computing, system tradeoffs and product requirements. In this role, youll work closely with Product to define the hardware requirements and an architecture to address them. Youll identify system level tradeoffs, identify solutions alternatives and define POCs to evaluate them. In your role youll be working closely with all R&D teams, in particular the system, hardware and logic teams and with partners in the industry.
Responsibilities:
Architecture for the next generation quantum control system and hardware
Define system-level architecture and features, providing detailed specifications to the various R&D teams.
Collaborate with the product and research to transform high level requirements into architecture and spec definitions and presenting tradeoffs
Collaborate with the architecture team members to consolidate requirements and implications for the software and logic architecture
Work with partners and vendors on requirements and joint development to optimize the product capabilities
Define requirements for research activities and for proof-of-concepts for new architecture and technical capabilities.

we are a global leader in control systems for quantum computing, a field on the verge of exponential growth.
Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands.
At the core of our company lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers.
Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field.
Join our cutting-edge hardware development team as Micro-Architect and play a key role in defining and implementing the micro-architecture of advanced digital logic components.
What You'll Do:
Define and develop micro-architecture for complex logic blocks - from concept through high-quality RTL implementation
Collaborate closely with architecture, verification, design and software design teams
Write clear and detailed design specifications and drive architectural trade-off analysis
Optimize for performance and area
Contribute to innovation, methodology improvements, and technical leadership within the team.

Were building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems.
If youre driven by solving problems, some dont yet have names, this is where you want to be.
In this role, you will:
Establish and lead a Back-End team with emphasis on RTL to GDS flow, Floorplan, Synthesis, Place and route, clock-tree, STA, layout, signoff (Timing, DRC, LVS) and Power
Be responsible for the Backend execution and methodologies
Be responsible to guide and lead contractors

Were building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems.
If youre driven by solving problems, some dont yet have names, this is where you want to be.
About The Position:
DFT (Design For Test) is a multidisciplinary field which involves many aspects of the chip design process, including: DFT architecture definition, RTL design, verification, backend implementation, STA, pre and post production activities and many more.
You will be part of a growing team that develops from scratch its DFT implementation flow and responsible for all DFT activities and you will closely work with multiple teams within the VLSI group.

Were building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems. If youre driven by solving problems, some dont yet have names, this is where you want to be.
In this role you will:
Develop and maintain all aspects of the emulation environment- Emulation model, Test plan, Validation environment
The Emulation engineer is involved in validation of significant aspects of ASIC development-chip performance, SW-HW API , system boot and functional flows
Expect to work closely and be part of the development process of the RTL design, verification, software development, testing, and more
Participate in design methodology and tool automation work as needed

Were building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems.
If youre driven by solving problems, some dont yet have names, this is where you want to be.
The role includes:
Be part of a founding BackEnd team and tackle greatest technology challenges.
Responsibility for RTL2GDS flow including Floorplan, Synthesis, Place and route, clock-tree, STA, signoff (Timing, DRC, LVS, EMIR)
Take part in the definition of the Backend execution and methodologies.