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Requied Full Chip CAD Physical Design Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The AI and Infrastructure team is redefining whats possible.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Demonstrate an understanding of the Register-Transfer Level (RTL) to Graphic Data Stream (GDS) II flow.
Manage the implementation of large, complex system-on-chips (SoCs), subsystems, and sub-wrappers, and demonstrate an understanding of associated issues and solutions.
Utilize floorplanning, power grid design, and place-and-route methodologies, and use Synopsys tools like Floorplan Compiler (FC) and Formality.
Exhibit an understanding of advanced node design (e.g., 5nm and below) and related optimization techniques.
Develop script in Synopsys TCL and Python.

Required Senior SoC Formal Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to build the best cloud in the world for our services and for our Cloud customers, by solving real world business issues of performance, cost, and scale, utilizing hardware, software, and system solutions. To better serve evolving cloud needs, we are establishing a team in Israel to develop custom chips for servers.
In this role, you will perform formal verification of design properties of complex ASIC designs. You will collaborate closely with design and verification engineers to define meaningful properties that capture the design intent of a logic block and constraints on its input stimulus. You will also help define and improve design and verification methodologies that allow you to achieve formal verification closure.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Plan the formal verification strategy and create the properties and constraints for complex digital design blocks.
Utilize formal property verification tools combined with formal verification closure techniques to verify properties and apply sign-off to blocks.
Pioneer and refine formal verification methodologies by systematically embedding AI tools to optimize verification accuracy.
Architect and implement reusable formal verification components.

We are looking for a Senior DSP Software Engineer who will lead design and implementation of our innovative signal processing algorithms on the industry cutting-edge target platform, consisting of embedded cores, DSPs, and dedicated accelerators.

What will you do:
Perform analysis, design, implementation and validation of innovative MIMO imaging radar algorithms for next generation ADAS and autonomous
vehicles on our target platform
Participate in SW architecture design and perform signal processing algorithm porting & optimization
Address real-time constraints in a challenging memory/compute bound framework
Be part of a goal-oriented workgroup and dynamic research & development environment
Work in close collaboration with CTO and SW architecture team

Required Senior Silicon DFT Lead
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.
Responsibilities
Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

Required CPU Design for Test Engineer, Cloud
About the job
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our platforms, we make our product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
In this role, you will be part of a varied team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design-for-Test (DFT) Engineer, you will play a crucial role in DFT design, and support devices of extreme complexity to production. You will be responsible for developing flows, automation, and methodology, executing DFT activities. You will be responsible for test vectors end-to-end, from generating DFT content on complex design, debugging to coverage goals, simulating it at gate level, sign-off DFT to tapeout, and debugging Si results.
Responsibilities:
Execute activities in the design, implementation, and verification of Design for Testing solutions for Application-Specific Integrated Circuit (ASICs).
Develop DFT strategy for array DFT, hierarchical DFT, Scan, and Automatic Test Pattern Generation (ATPG).
Perform ATPG, scan coverage debug and drive design fixes for coverage and quality improvements.
Perform DFT verification at RTL and gate level.
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT design requirements are met and mutual dependencies are managed.

Required Senior Silicon Physical Design Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
Responsibilities
Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.
Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.

Required Signal/Power Integrity Engineer, PhD Graduate
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities:
Simulate high speed interface electrical behavior using HSPICE or other circuit simulators.
Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.
Collaborate extensively with cross-functional teams, including ASIC architects, digital/analog designers, physical design/layout engineers, and system engineers, to define specifications and resolve integration challenges.
Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR) , Spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.
Establish robust design rules and guidelines for optimal signal/power integrity during PCB and package layout, ensuring high production yield and reliability.

Required RTL Design Technical Lead, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use the ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead the Design Activities at IPs, SubSystems(S.S) and SoC.
Plan, execute, track progress, assure quality, report status of the assigned activity.
Lead a team of designers both directly and in teams.
Define the Block/SoC level design documents such as Micro Architectural Specifications.
Own IP, S, SoC strategies for clocks, resets, and debugs. Enforce global methodologies and drive enhancements.

Required Senior Edge-AI SoC Formal Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Pioneer and refine formal verification methodologies by systematically embedding AI tools to optimize verification accuracy.
Plan the formal verification strategy and create the properties and constraints for complex digital design blocks.
Utilize formal property verification tools combined with formal verification closure techniques to verify properties and apply sign-off to blocks.
Architect and implement reusable formal verification components.

Required CPU Core Micro Architect
Job Description
Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Micro architect will take charge in defining a processor Micro architecture features that will improve the performance and reduce the power consumption of the CPU core. This architect will use a performance simulator to explore his ideas and will analyze implementability of these features: Power, Timing, Area. This architect will utilize his processor and VLSI design experience to develop many advanced features for Huawei processors.

Required Wafer-Scale System: Computation (LLM) and Communication (NoC) Co-Design
In this job opening, we are seeking a highly motivated and visionary researcher to join our team focused on chiplet-based computing systems. This role involves research and development in chiplet-based architectures, aiming to overcome performance and scalability limits of traditional compute platforms.
Responsibilities:
Conduct cutting-edge research on the co-design of communication and computation for wafer-scale systems. On the communication side, the work focuses on architecting Networks-on-Chip, providing scalable, high-bandwidth, and ultra-low-latency interconnects that efficiently span multiple dies and support fine-grained data movement. On the computation side, the research emphasizes optimizing and mapping training and inference workloads to fully exploit wafer-scale resources, improving performance, scalability, and energy efficiency through intelligent task placement and scheduling.
Investigate various aspects of system design, including:
Network-on-Chip design, further including Topology exploration, routing algorithms, and protocol/flow-control design to support high-throughput collective communication, low-latency synchronization, and efficient model/data parallelism
Expressing and Mapping LLM Parallelism to Wafer-Scale System that simplify LLM parallelism (e.g., tensor, pipeline, and data parallelism) and efficiently map training and inference workloads onto wafer-scale system.

We are looking for a highly analytical, detail-oriented Innovation Expert to join our Open Innovation team. This role is ideal for candidates who sit at the intersection of deep tech, startup ecosystem and academy, possessing strong technology analytical skills, clear communication, and a foundational background in computer architecture research.
In this role, you will drive our external innovation strategy by managing academic research collaborations, scouting early-stage deep-tech startups and conducting technical due diligence.
Key Responsibilities:
Academic Cooperation & Research Partnerships: Identify and build direct collaboration agreements with world-class professors, research labs, and universities. Facilitate joint research projects, tech-transfer initiatives, and track academic spin-offs.
Startup Scouting & Ecosystem Mapping: Actively identify, source, and map early-stage deep-tech startups and emerging tech companies globally within the companys strategic domains.
Technical Due Diligence: Evaluate startup technologies, product-market fit, and team capabilities. Analyze technical validity and assess how external innovations align with our internal roadmaps.
Ecosystem Analysis: Conduct deep-dive analyses of startup ecosystems, venture capital trends, and academic spin-offs to identify high-potential investment and collaboration opportunities.
Investment & Collaboration Support: Synthesize technical and commercial findings into clear, structured scouting reports, investment tech memos, and presentations for senior leadership to drive partnership or investment decisions.
Cross-Border Collaboration: Act as a bridge between startup founders, academic innovators, and internal global teams (including European and China-based business units) to facilitate joint POCs, or investment reviews.
Track Tech Domains: AI infrastructure, advanced semiconductors, hardware-software co-design, and AI data movement.

Semi Conductor Devices (SCD), a worldwide leader of high-end Infrared Detectors and thermal video cores, is seeking a Senior Digital VLSI Engineer to participate in the definition, design, verification, implementation, and silicon validation of next-generation infrared image sensors. Responsibilities • Be part of a team defining future Image Sensor Digital controller Architecture • Participate in the digital design and verification effort of state-of-the-art IR Image Sensors, working closely with the Analog designers and Board designers (internal and external interfaces) • Take part in ASIC development lifecycle (pre- and post-silicon) – from Spec definition to block-level design, full-Chip till Silicon Validation in the laboratory and customer support • Lead the design and integration of complex digital blocks from specification to silicon • Drive VLSI innovation and integration of new technologies into projects and activities in the design organization

We are looking for an Algorithms Developer to join the CTO Office and develop and evaluate new AI and algorithmic capabilities as part of early-stage R&D. The role combines hands-on algorithm development, rapid prototyping, and technical evaluation, from exploring new ideas and testing solutions to defining requirements for further development. Projects span areas such as image processing, computer vision, edge AI, LLM-based applications, and emerging technologies.
Responsibilities:

* Develop AI and algorithmic solutions for early-stage R&D projects.
* Translate project needs into algorithmic concepts, requirements, and technical solutions.
* Build and TEST prototypes to evaluate feasibility and performance.
* Define performance, interfaces, and computing requirements.
* Optimize solutions for compute, memory, power, and latency constraints.
* Evaluate relevant models, frameworks, hardware platforms, and emerging technologies.
* Translate R&D results into clear requirements and recommendations for development teams.
Advantages:

* Experience deploying AI or algorithms on edge or Embedded platforms.
* Experience with NVIDIA, CUDA, TensorRT, ONNX, or similar technologies.
* Experience optimizing algorithms for compute, memory, power, or latency.
* Experience with satellite imagery, remote sensing, geospatial applications, mapping, or photogrammetry.
* Experience with LLM-based applications and modern AI frameworks.
* Experience in R&D, advanced development, or deep-tech environments.

As a Digital Backend Design Engineer, you will be responsible for the physical implementation of digital designs from RTL to GDSII, leveraging cutting-edge EDA tools and methodologies. You will collaborate closely with RTL design, DFT, and packaging teams to achieve optimal performance, power, and area (PPA), while meeting stringent timing and yield targets.

Required Skills and Experience
Masters or PhD degree in Electrical/Electronic Engineering or a related field.

4+ years experience in digital IC backend implementation.

Proficiency with backend EDA tools, particularly Cadence Innovus and Genus.

Strong understanding of place & route (P&R), static timing analysis (STA), DRC/LVS verification, IR drop, and electromigration (EM) analysis.

Experience with advanced technology nodes (22nm or below preferred).

Skilled in Tcl scripting for automation of backend flows.

Experience in hierarchical or full-chip implementation is preferred.

Language: English at a proficient level. French is a plus.