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We are looking for an experienced SoC architect to join our team for next generation product line. You will collaborate closely with cross-functional teams (software, firmware, and system engineers) to develop, verify, and use performance models for data-driven architectural exploration and validation. You will be a key contributor to our technology roadmap and help drive innovation in our hardware solutions.

Role Overview:
We are launching new team that will be responsible to define and architect our next generation communication platform.
We are looking for a candidate that he is go to person to get things done, excellent interpersonal skills, data driven oriented and highly motivated.

A company of inventors that unlocked 5G - ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.

This role can be based in either Hod HaSharon or Haifa.
As an RTL Design Engineer, you would be responsible for one or more functional units of the micro-controller and application processor, while working closely with architecture, verification, modeling, validation, and implementation teams to meet all functional requirements and performance, power, area (PPA) goals.
An ideal candidate will have at least 10 years of work experience in microprocessor, SoC, memory controller and interconnect IP design.

we are looking for a Customer Success Technical Engineer
What will you do?

Own the end-to-end technical customer experience from installation to ongoing support with a strong focus on on-site and remote service excellence.
Lead system installation, configuration, testing, and customer training at global customer sites.
Act as the technical focal point for both customers and internal teams, identifying technical issues, trends, and improvement opportunities.
Escalate and drive resolution of complex technical cases in collaboration with Engineering, Operations, and Product teams.
Ensure customer feedback and field insights are shared and reflected in product and service improvements.
Collaborate closely with global service teams, R&D, and Product to resolve challenges and ensure customer success.
Contribute to the creation of service guides, technical documentation, and internal knowledge-sharing initiatives.
Travel globally up to 50% of the time for on-site installations, training, and technical support.

Job Description: We are seeking a highly skilled and experienced Automated TEST Equipment Engineer to join our dynamic team. You will be responsible for the design, development, and implementation of automated TEST systems for our cutting-edge products. This role requires a strong background in hardware engineering, as well as experience in TEST automation and system integration. Responsibilities:
* Design and develop hardware solutions for automated TEST systems, including TEST fixtures, load boards, and interface circuits.
* Perform hardware debugging, troubleshooting, mass production support and optimization to ensure reliable and efficient TEST systems.
* Develop and maintain hardware documentation, including schematics, layouts, and mechanical designs.
* Design and develop software for TEST automation, including TEST sequencing, data acquisition, and result analysis.
* Collaborate with cross-functional teams, including hardware, software, engineering, quality, and manufacturing.
* Stay up to date with the latest trends and technologies in automated testing procedures.

We seek an Embedded Software Engineer to join our R&D team.
As our Embedded Engineer, you will work closely with hardware engineers to create efficient, reliable, and scalable embedded solutions for various applications.
A day in the life and how youll make an impact:
Design, develop, and test firmware for microcontrollers and embedded systems.
Collaborate with hardware engineers to ensure seamless integration between software and hardware components.
Debug and troubleshoot embedded systems using oscilloscopes, logic analyzers, and other debugging tools.
Develop and maintain technical documentation, including software architecture and design specifications.
Implement communication protocols such as SPI, I2C, UART, Ethernet

We are looking for a Senior QA Engineer to join our QA R&D team and become an expert in UVeyes products, ensuring they meet all system requirements and specifications.
A day in the life and how youll make an impact:
Become a key member of the UVeye QA team, gaining deep expertise in our products.
Lead end-to-end testing for new features and software releases, from Test Plan definition to release execution and post-release monitoring.
Collaborate with R&D teams (Software & Algorithm) to deliver high-quality features that meet customer expectations.
Contribute to the design, testing, and execution of automated testing capabilities.
Participate in Agile development processes using Jira, including daily stand-ups, planning, demos, and retrospectives.

Design and develop TEST plans for VLSI circuits, including digital, analog, and mixed-signal circuits. Implement and execute TEST procedures to ensure the functionality and performance of VLSI circuits. Analyze TEST data and identify issues related to circuit design, manufacturing, and performance. Collaborate with design engineers to develop and optimize TEST methodologies. Develop automated TEST scripts and tools to improve TEST efficiency and coverage. Perform failure analysis and debug issues to identify root causes and implement corrective actions. Document TEST results, methodologies, and procedures for future reference. Stay updated with the latest advancements in VLSI testing technologies and methodologies.

we are looking for a highly skilled and experienced DFT Lead to take a central role in shaping the DFT implementation for the companys next-generation SoC. As the DFT Lead, you will be responsible for overseeing the development and execution of testing methodologies to ensure the functionality, reliability, and manufacturability of integrated circuits (ICs) and other hardware designs. You will play a critical leadership role in integrating test structures into the design of electronic components, driving efficient testing processes throughout the product lifecycle, from production to deployment and maintenance. This is a key position that will directly influence the success of our projects and the quality of our products.
Responsibilities
Develop DFT methodologies for IC designs, such as scan chains, built-in self-test (BIST), boundary scan, MBIST
Implement and validate DFT features to ensure coverage and quality.
Perform scan insertion, MBIST insertion and ensure architectural spec is met
Generate ATPG patterns for stuck at and at speed, ensure all sequential elements are scannable to achieve high coverage. Generate MBIST patterns and ensure all memories are being covered for defects
Collaborate with design teams to create test strategies and plans that identify potential defects
Perform simulations and verification of DFT designs to confirm functionality and accuracy.
Analyze fault models and optimize for high coverage, including stuck-at, transition, and path delay faults.
Collaborate with test engineers to perform yield analysis and improve DFT methodologies.
Troubleshoot and debug design issues found during testing.
Develop techniques to isolate faults and improve test coverage with minimal impact on design.
Work with cross-functional teams (e.g., design, verification, test engineering) to integrate DFT features effectively.
Document DFT architecture, procedures, and test coverage to support production testing and ongoing improvement.

Required Experienced DFT Engineer
The EyeC VLSI team designs cutting-edge chips for RADAR systems used in ADAS and autonomous vehicles and is looking for an experienced DFT Engineer.
This is a unique opportunity to join a team of top-tier engineers working with the most advanced technologies to develop Autonomous Vehicle (AV) SoCs. Every engineer in our team plays a broad and diverse role, taking on significant responsibilities, being involved in critical development stages, and making a direct impact on the success of our projects.
What will your job look like:
You'll be responsible for the architecture of DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary RTL for the different modules
Verify and Validate your design in GLS
Develop ATPG patterns to the highest requirements of Functional Safety (ISO26262).
Debug and analyze coverage and yield loss
Support production activities and Si debug.

The EyeC VLSI team designs cutting-edge chips for RADAR systems used in ADAS and autonomous vehicles and is looking for an experienced DFT Engineer.
This is a unique opportunity to join a team of top-tier engineers working with the most advanced technologies to develop Autonomous Vehicle (AV) SoCs. Every engineer in our team plays a broad and diverse role, taking on significant responsibilities, being involved in critical development stages, and making a direct impact on the success of our projects.
What will your job look like:
You'll be responsible for the architecture of DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more)
Develop all the necessary RTL for the different modules
Verify and Validate your design in GLS
Develop ATPG patterns to the highest requirements of Functional Safety (ISO26262).
Debug and analyze coverage and yield loss
Support production activities and Si debug.

Were looking for a Physical Design Expert to join the growing Physical Design Team, responsible for developing our next generation Imagining Radar SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS with horizontal ownership.
Floorplan exploration and collaboration with front-end and architecture teams.
Synthesis exploration and final synthesis including: SDC definition, Scan insertion, Lint, LEC, UPF-LP & Spyglass verification.
Place & Route: from Synthesis to final layout and signoff verification on all tools and floors, with target to achieve best PPA.
STA: timing analysis, working with Sub System and Full Chip owners to manage block and top level constraints for synthesis, P&R and signoff.
Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.