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18/09/2025
Location: Tel Aviv-Yafo
Job Type: Full Time
we are a global leader in hybrid control systems for quantum computing, a field on the verge of exponential growth.
Our innovative hardware and software offer a groundbreaking approach to controlling quantum computers, scaling from individual qubits to arrays of thousands.
At the heart of QM is a passionate, ambitious team committed to transforming the construction and operation of quantum computers. Our deep understanding of customer needs drives us to deliver unmatched solutions in this revolutionary field.
We are looking for a highly experienced a hands-on Compiler Engineer who embodies ambition and positivity.
Someone who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfill the evolving needs of our expanding customer base.
Requirements:
Responsibilities:
Develop QM's compiler from a proprietary quantum language to a proprietary processor tailored to realize and accelerate quantum computing.
Take on complex optimization challenges at the core of our unique compiler, focusing on real-time applications, hybrid quantum/classical algorithms, and parallel processing.
Conduct rigorous testing, debugging, and profiling to ensure the performance and correctness of compiler outputs.
Hands-on development and debugging of software to optimize the utilization of limited hardware resources, enabling the scaling of quantum computing systems and improving quantum algorithm performance on our cutting-edge quantum orchestration platform.
Collaborate closely with hardware, software and architecture teams to ensure seamless software-hardware integration, directly enhancing system capabilities and performance.
Requirements:
At least 5 years of hands-on programming experience Must.
BSc. in Computer Science, Computer Engineering, Mathematics, or any relevant scientific field (advanced degrees are an advantage) - Must.
Experience in computer architecture, assembly language, and low-level programming concepts Advantage.
Experience working in a multidisciplinary environment Advantage.
Familiarity with MLIR/LLVM Advantage.
A motivated and resourceful problem solver with a passion for tackling complex technical challenges, especially in hardware-oriented environments.
This position is open to all candidates.
 
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18/09/2025
Location: Tel Aviv-Yafo
Job Type: Full Time
we are a global leader in control systems for quantum computing, a field on the verge of exponential growth.
Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands. At the core of QM lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers.
Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field.
We are looking for a highly experienced Logic Design Engineer who embodies ambition and positivity. Someone who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfill the evolving needs of our expanding experienced DevOps Engineer customer base.
Join us in this exciting journey to redefine the future of quantum computing.
Requirements:
Responsibilities:
Learning system and SW requirements for proper implementation of HW-SW interface
Designing a configurable and very low-latency challenging RTL
Bringing the state-of-the-art FPGA to its limits with regards to logic & timing optimization
End2end ownership of the entire coding process (Arch->uArch->Design->Implementation)
Requirements:
BSc in electrical/computer engineering or relevant military background- Must
At least 7 years of experience- Must
Proven track record in RTL coding with System Verilog- Must
Experience with System Verilog- Must
VCS, Vivado - Advantage.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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18/09/2025
Location: Tel Aviv-Yafo
Job Type: Full Time
we are a global leader in control systems for quantum computing, a field on the verge of exponential growth.
Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands.
At the core of QM lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers.
Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field.
Join our cutting-edge hardware development team as Micro-Architect and play a key role in defining and implementing the micro-architecture of advanced digital logic components.
What You'll Do:
Define and develop micro-architecture for complex logic blocks from concept through high-quality RTL implementation
Collaborate closely with architecture, verification, design and software design teams
Write clear and detailed design specifications and drive architectural trade-off analysis
Optimize for performance and area
Contribute to innovation, methodology improvements, and technical leadership within the team.
Requirements:
B.Sc. or higher in Electrical Engineering, Computer Engineering, or related field- Must
8+ years of experience in RTL design using Verilog/SystemVerilog- Must
Proven experience in designing micro-architecture for complex systems
Strong system-level understanding and problem-solving skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8352548
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Location: Ra'anana
Job Type: Full Time
We are seeking an experienced and highly motivated Engineering Manager to establish and lead a new engineering function for our growing software organization as we build out our product design and production capabilities.
The Engineering Manager will be responsible for building and leading Engineering team and will be responsible for seamless transition of R&D prototypes into manufacturing, ensuring quality, manufacturability, testability and cost-effectiveness throughout product lifecycle. This individual will play a key role in collaborating with R&D, quality, supply chain, and our contract manufacturers to deliver high-quality products within time to market efficiently.
Responsibilities:
R&D Transfer & Manufacturability:
Lead the process of transferring product prototypes from R&D to mass production, ensuring all necessary documentation, specifications, and processes are in place.
Collaborate with R&D on functionality and manufacturability of new products, providing engineering support. (DFM/DFA)
Product Engineering & Lifecycle Management:
Build PLM, BOM define data item attributes, later transfer to NPI Engineer
Build an engineering team, own all engineering aspects of products from prototype to mass production.
Manage / partner with RD for component selections / component engineering to meet the applicable standards
Maintain engineering documentation, including schematics, layouts, mechanical designs, and test procedures, manage Eng changes throughout product lifecycle (ECO/MCO/DA)
Manage Approved Vendor List (AVL) for all products
Responsible for product quality, and quality within operations, RD on ongoing product quality and reliability
Manufacturing & Supplier Support:
Support contract manufacturers (CMs), troubleshooting production issues, and ensuring adherence to quality standards.
Collaborate with CMs on process optimization, yield improvements, and failure analysis
Establishing and support ATE (JTAG, FT, ICT) within production assembly lines
Team Leadership & Development:
Build and mentor a team of product engineers as the organization grows.
Establish the best practices and engineering processes for product development, transfer, and lifecycle management.
Requirements:
Bachelors degree in electrical / computer engineering, Mechanical Engineering, or related technical field.
5+ years experience in engineering in companies with hardware products (communications, is advantage) working closely with development teams. Proven experience as engineering manager.
Strong knowledge of manufacturing processes for electronic and mechanical assemblies, preferably experience in PCBA and SMT assembly
Proven experience with successfully transitioning NPI products from R&D to mass production
Deep understanding of Design for Manufacturability (DFM), Design for Assembly (DFA), and Design for Testability (DFT) principles.
Proven responsibility for product quality, familiar with quality processes (CAPA, 8D, RCA)
Experience in BOM management, configuration control, AVL, engineering change (ECO/MCO/DA) processes familiar with product lifecycle management (PLM) systems / Agile is advantage.
Knowledge / familiar with ATE Testers (ICT/JTAG/FT)
Background / Knowledge in component engineering
Exceptional communication and interpersonal skills, with the ability to effectively collaborate with diverse teams and external partners.
Ability to work independently and manage multiple projects simultaneously in a fast-paced environment
Experience for building engineering team from scratch is an advantage.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8351721
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Haifa
Job Type: Full Time
Were looking for a System Engineer to join our multidisciplinary R&D team and help define the system architecture, integration, and design of innovative medical devices in oncology.

In this role, you will:
Lead system design and requirements definition for complex hardware-software systems.
Collaborate with cross-functional teams, including product, engineering, QA, and regulatory.
Analyze design alternatives, manage system-level integration, and support V&V processes.
Ensure compliance with medical device standards and contribute to technical decision-making.
Requirements:
BSc in Engineering or Science (preferably Computer or Electrical).
Proven experience of at least 5 years as a development engineer (software or hardware) in multidisciplinary systems.
Minimum of 4 years of proven experience as a System Engineer in multidisciplinary systems, preferably in a regulated environment.
Proven experience in defining system requirements, architecture, and integration.
Strong communication skills and ability to lead technical discussions.
Experience with medical devices an advantage.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
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8350869
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v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
16/09/2025
Location: Tel Aviv-Yafo
Job Type: Full Time
Storage Service (S3) and Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWSs services and features apart in the industry. As a member of the UC organization, youll support the development and management of Compute, Database, Storage, Internet of Things (IoT), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services.

Annapurna Labs, as part of AWS, is looking for an experienced engineer, to help us develop our cutting-edge semiconductor platform.
Youll have the opportunity to join a top-tier, agile, fast-paced team, and take part in the development of the technology that powers the worlds largest cloud provider.
Web Services offers a highly reliable, scalable, low-cost cloud platform that enables hundreds of thousands of businesses in 190 countries around the world.
We are looking for talented people to join the Chip Design team in TLV,
Take an active, significant part in developing the next generations of products that will enable AWS to be the lead in the Cloud sector.

Key job responsibilities
Full ownership of one or more IPs within the product:
-Micro-architecture
-RTL coding and debug
-Synthesis and timing closure
-Sign-off
Supporting the Verification and Emulation teams: Test plan, Coverage review
Ensuring that the chip meets quality and reliability standards.
Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical design
values diverse experiences. Even if you do not meet all of the preferred qualifications and skills listed in the job description, we encourage candidates to apply. If your career is just starting, hasnt followed a traditional path, or includes alternative experiences, dont let it stop you from applying.
Why AWS
Web Services (AWS) is the worlds most comprehensive and broadly adopted cloud platform. We pioneered cloud computing and never stopped innovating thats why customers from the most successful startups to Global 500 companies trust our robust suite of products and services to power their businesses.
Work/Life Balance
We value work-life harmony. Achieving success at work should never come at the expense of sacrifices at home, which is why flexible work hours and arrangements are part of our culture. When we feel supported in the workplace and at home, theres nothing we cant achieve in the cloud.
Inclusive Team Culture
AWS values curiosity and connection. Our employee-led and company-sponsored affinity groups promote inclusion and empower our people to take pride in what makes us unique. Our inclusion events foster stronger, more collaborative teams. Our continual innovation is fueled by the bold ideas, fresh perspectives, and passionate voices our teams bring to everything we do.
Mentorship and Career Growth
Were continuously raising our performance bar as we strive to become Earths Best Employer. Thats why youll find endless knowledge-sharing, mentorship and other career-advancing resources here to help you develop into a better-rounded professional.
Requirements:
B.Sc. in Electrical Engineering/Computer Engineering
5+ years of experience in Chip Design
Experience working with data paths
PREFERRED QUALIFICATIONS
Experience with large scale IPs (Millions of gates)
Experience with a full design cycle RTL/Verification/Synthesis and timing closure/CDC/ Lint.
Experience with Networking layers
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing Application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.
You will also be responsible for performance analysis for a networking stack.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our customes, Cloud customers and the billions of people who use our companyservices around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead an ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Implement designs in SystemVerilog.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience architecting networking ASICs from specification to production.
Experience developing RTL for ASIC subsystems.
Experience in micro-architecture, design, verification, logic synthesis, and timing closure.
Preferred qualifications:
Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science.
Experience architecting networking switches, end points, and hardware offloads.
Experience working with design networking like: RDMA or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience with Mastery of TCP, IP, Ethernet, PCIE, and DRAM, and familiarity with Network on Chip (NoC) principles and protocols (e.g., AXI, ACE, and CHI).
Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.
Ability to adeptly estimate performance through analysis, modeling, and network simulation, and drive performance test plans.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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דיווח על תוכן לא הולם או מפלה
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סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our customers, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Build C/C++ firmware running on embedded processors with limited memory footprints on the SoCs.
Develop tools to update and debug the firmware, enable emulation, chip bringup, and hardware debugging.
Play key roles in emulation, chip bring up, and SoC deployment, and contribute to all layers of the data center software stack to deploy SoCs to production.
Create code generators to generate C++ code based on hardware specifications.
Requirements:
Minimum qualifications:
Bachelor's degree in Computer Science, Computer Engineering, a related technical field, or equivalent practical experience.
1 year of experience coding in C/C++.
Experience with embedded systems/firmware design.
Experience working with networking (e.g., Remote Direct Memory Access (RDMA)) or packet processing and system design principles.
Preferred qualifications:
Experience with hardware design (e.g., computer architecture or chip design).
Experience with SoC cycles.
Ability to work with device level hardware and software, especially in a lab environment.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8345214
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our company platforms, we make our company's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest our company possible.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our customers , Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Design, develop, test, deploy, maintain, and improve SOC software modeling and other software tools.
Manage individual project priorities, deadlines, and deliverables.
Collaborate with hardware and software architecture teams, SOC performance modeling team, and other company software teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
5 years of experience with software development in C++, and with data structures/algorithms.
Experience in performance modeling, performance analysis, and workload characterization.
Preferred qualifications:
Masters degree or PhD in Engineering, Computer Science, or a related technical field.
4 years of experience with performance, systems data analysis, visualization tools, or debugging.
Experience in modern, high-performance Networking architecture and micro-architecture.
Ability and interest to learn other coding languages as needed.
Excellent object-oriented, database design, and SQL skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8345067
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a CPU Design Verification Engineer, you will work as part of a Research and Development team building verification components, constrained-random testing, system testing, and verification closure. As part of our server chip design team, you will verify complex digital designs. You will collaborate with design and verification engineers in active projects and perform verification. You will be responsible for the full lifecycle of verification which can range from verification planning, test execution, or collecting and closing coverage.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our company platforms, we make our company's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Apply close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
Experience creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at Register Transfer Level (RTL) level using SystemVerilog or Specman/E for Field Programmable Gate Arrays or ASICs.
Preferred qualifications:
Masters degree in Electrical Engineering or Computer Science.
Experience with Universal Verification Methodology (UVM), SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
Experience with CPU implementation, assembly language, or compute SOCs.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8345046
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סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our customers, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define and implement solutions for design, integration and verification problems using in-house and external technical solutions or tools. Ensure chip quality by implementing best practices and implementing quality control measures.
Participate in project development and convergence with the highest quality, and manage issues as they arise through design and implementation.
Connect between RTL design, physical design, Design for Test (DFT), external IPs and SoC while maintaining project priorities.
Maintain project infrastructure and stability.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
4 years of experience with design from microarchitecture through implementation with Verilog/SystemVerilog, or VHDL language.
Experience with scripting.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC).
Experience with Synthesis, SDC, DFT, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation.
Experience with chip design flow, physical design, IP integration, and Design for Testing (DFT).
Ability to multitask, with excellent communication and facilitation skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8345026
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use your ASIC design experience to be part of a team that develops the ASIC SoC from Plan of Record (POR) to Production. Creating SoC Level micro architecture definitions, RTL coding and all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies. You will collaborate with members of architecture, software, verification, power, timing, synthesis dft etc. You will face technical tests and develop/define design options for performance, power and area.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our customers, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Participate in architecture feedback.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
Experience in logic design.
Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
Experience with design sign off and quality tools (e.g., Lint, CDC, etc.).
Experience with SOC architecture.
Preferred qualifications:
Master's degree or PhD in Computer Science or a related technical field.
Knowledge of assertion-based formal verification.
Knowledge in one of these areas: Peripheral Component Interconnect Express (PCIe), Universal Chiplet Interconnect Express (UCIe), Double Data Rate (DDR), Advanced eXtensible Interface (AXI), or Advanced RISC Machines (ARM) processors family.
Knowledge of high performance and low power design techniques.
Excellent problem-solving and debugging skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8344984
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our customers, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Define and implement solutions for design, integration and verification problems using in-house and external technical solutions or tools. Ensure chip quality by implementing best practices and implementing quality control measures.
Participate in project development and convergence with the highest quality, and manage issues as they arise through design and implementation.
Connect between RTL design, physical design, Design for Test (DFT), external IPs and SoC while maintaining project priorities.
Maintain project infrastructure and stability.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
8 years of experience with design from microarchitecture through implementation with Verilog/SystemVerilog, or VHDL language.
Experience with scripting.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with ASIC design methodologies for front quality checks (e.g., Lint, CDC/RDC).
Experience with Synthesis, SDC, DFT, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation.
Experience with chip design flow, physical design, IP integration, and Design for Testing (DFT).
Ability to multitask, with excellent communication and facilitation skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8344980
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our company platforms, we make our company's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.
Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience with System on a Chip (SoC) cycles.
Experience with advanced design, including clock/voltage domain crossing, DFT, and low power designs.
Experience in high-performance, high-frequency, and low-power designs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with scripting languages such as Perl, Python, or Tcl.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8344975
סגור
שירות זה פתוח ללקוחות VIP בלבד
סגור
דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing ASICs used to accelerate networking in data centers. You will have dynamic, multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.
You will be responsible for performance analysis for an end-to-end networking stack using your knowledge.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users are our customers, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead a complex ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement data center networks.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience architecting networking ASICs from specification to production.
Experience developing RTL for ASIC subsystems.
Experience with cross-functional engagement in micro-architecture, design, verification, logic synthesis, and timing closure.
Preferred qualifications:
Experience working with software teams optimizing the hardware/software interface.
Experience working with design networking like: Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience in TCP, IP, Ethernet, PCIE and DRAM including Network on Chip (NoC) principles and protocols (AXI, ACE, and CHI).
Experience architecting networking switches, end points, and hardware offloads.
Understanding of packet classification, processing, queuing, scheduling, switching, routing, traffic conditioning, and telemetry.
Proficiency in a procedural programming language (e.g. C++, Python, Go).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8344963
סגור
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