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We are a highly experienced architecture group specializing in switch processing, with deep expertise in both hardware and software architecture in the high-speed networking domain.
Our innovative packet processors power some of the most advanced data centers in the world and are designed into tier-1 vendor platforms. With state-of-the-art technology, a strong track record of industry recognition, and multiple award-winning achievements, we continuously push the boundaries of performance and scalability.
Our group is involved across the entire development lifecycle - from early research and architectural definition to silicon production - working on both research initiatives and production-grade products.
our Impact
As HW Architect Team Leader, you will combine deep technical leadership with people leadership. You will shape next-generation networking silicon while building and mentoring a strong architecture team.
What Youll Be Doing
Lead, manage, and mentor a team of HW architects, fostering technical excellence and innovation.
Drive research, evaluation, and architectural definition of next-generation SoCs - from product requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet and NIC switches.
Lead system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate cross-functionally with design, verification, modeling, software, and other architecture teams to ensure end-to-end system alignment.
Identify and evaluate new technologies, methodologies, and architectural approaches for future products.
Provide technical direction, make key architectural trade-offs, and ensure execution excellence.

About the group:
We are a highly experienced architecture group specializing in switch processing, with deep expertise in both hardware and software architecture in the high-speed networking domain.
Our innovative packet processors power some of the most advanced data centers in the world and are designed into tier-1 vendor platforms. With state-of-the-art technology, a strong track record of industry recognition, and multiple award-winning achievements, we continuously push the boundaries of performance and scalability.
Our group is involved across the entire development lifecycle - from early research and architectural definition to silicon production - working on both research initiatives and production-grade products.
What will you be doing?
Lead research, evaluation, and architectural definition of next-generation chips - from requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet Switches.
Design the system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate closely with design, verification, and modeling teams to ensure architectural intent is fully realized.
Work cross-functionally with other architecture teams to shape cohesive system solutions.
Explore and evaluate new technologies and innovative approaches for future products.

We are currently looking for a Performance Simulation Expert develop and evaluate next generation performance features as well as develop the future generation of our Compute system simulation infrastructure, models and analysis tools
Responsibilities:
Develop and analyze performance and power features in our cycle accurate pre-silicon model and improve the accuracy of the current Server system simulator
Design the architecture of the new generation system simulation platform that will be used to analyze performance of Server (Compute and AI) workloads and identify performance bottlenecks
Develop new technologies, methodologies and tools for simulation. Analysis and debug of applications and workload on Huawei servers
Propose and simulate optimizations and innovations on the HW and SW in order to improve server performance for given workloads
Distribute the simulation platform, train and support other teams in China and in Europe using the simulation platform, technology and methodology.

Looking for a CPU performance modeling architect to take responsibility over the performance aspects of new CPU instructions or modes of operation. The role includes but is not limited to:
Partners with lead SW and HW architects to co-invent optimal HW and SW solutions that come to address requirements. Influences the direction based on experiments and simulation data
Models CPU functionality, performance and/or power in pre-silicon simulators
Defines and runs performance experiments to aid feature definition. Such experiments can be performed on a pre-silicon simulation environment or in a real system or on a combination of both or even in combination with analytical models
Provides experimental/proof of concept for new features and implementation alternatives meeting performance constraints.
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usages
Potentially (in the future), lead a team doing above activities
An adequately qualified candidate can also become the leader of definition for some features in addition to all the roles above.

Looking for a CPU Architect for codesign of HW/SW feature for our CPUs for cellphones and servers. The role includes but is not limited to:
Analysis of technical challenges and determination of whether to solve them by a combination of new HW and new SW or by only one of these
Invents corresponding HW features and SW solutions to address above challenges. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for CPU. Develops the end-to-end architecture of new instructions (when applicable) in coordination with partners. Drives the inclusion of the feature in a CPU project working with micro-architects, designers and verification experts. (the HW/SW features are typically in the form of new instructions or of other Instruction Set constructs and belong to one of following domains: dense compute, general purpose accelerations, use case specific accelerations, system level instructions, Security related technologies, or instrumentation instructions.
Models CPU functionality, performance and power in simulators, analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage.
Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.
Reviews and influences cross functional roadmaps.
Collaborates with SW and HW architects, design, verification, and validation engineers during the execution of the project. Finds mitigations for issues that arise during implementation of his/her features.

Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Architect will take charge of defining a processor on chip inter-connect and coherent fabric that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

TEST verification and validation (both hw and sw).
maintain products quality by improving TEST stability, coverage, design, and manufacturing process.
execute tests in different scopes such: regression, performance degradation, functional, and security; report the progress of testing and provide summary reports of the activity.
troubleshooting and streamlining/optimizing our testing procedures.
support production matters.

we are looking for a creative and independent senior TEST engineer. nvidia networking unit has continuously reinvented itself over two decades. our high-speed buses & network products are leading in the markets with innovative ways to improve speed and bandwidth from one generation to another. today, nvidia is increasingly known as the place for getting end-to-end high-speed ethernet and infiniband solutions we're looking to grow our company and build our teams with people who can join us at the forefront of technological advancement. we need a creative individual who will help transfer network silicon ics products (switch, nic, smartnic) from design engineering to mass production.
you will be exposed to various aspects of design, dft and TEST of nvidia network ic products, and will be responsible for definition and development of tests from wafer level to final TEST of network-ics. in addition, your responsibilities will include working with overseas manufacturing teams to increase yields, TEST coverage and capacity, and reduce production costs. if you are passionate about enabling of the highest quality network products that will change the world, we want to hear from you!
what you'll be doing:
ic TEST definition & development
write, execute and debug fw code
manage failure analysis of field and production failures
provide dft recommendations to the design teams
build expertise on production of network products

responsibility to coordinate between all project collaborators such as chip design team, q&r team, arch, icpe, from initial fuse definition stage till product end of life, including release to mass production
responsibility for all fuse ccb activities
collaborate closely with domain owners and stakeholders across various teams to gather and validate inputs required for product configuration, ensuring alignment with overall project and product strategies.
manage and coordinate configuration files and parameters for multiple products, maintaining accuracy and consistency throughout the product lifecycle.
contribute hands-on to product execution activities by actively working on configuration management, including updates, troubleshooting, and validation of configuration settings
support the integration of product configurations into the overall product development and manufacturing processes, ensuring smooth deployment and operational readiness across multiple product lines

you will be developing physical design, sta, logic eq, power integrity flows and methodologies for implementation of networking chips and socs.
work closely with block owners, full chip sta engineers to assure high quality and timely convergence.
come up with unique and creative solutions to the state of the art physical design problems that are needed for our chips.
additional responsibilities include participating and developing flow and tool methodologies for timing analysis and closure, power and noise analysis, ir-drop, em and back-end verification across multiple projects.

we are looking for a talented experienced firmware engineer to join our network adapter firmware team. the firmware team develops cutting edge networking features for cloud, hpc and Storage. we drive the data growth of the worlds biggest companies. with talented engineers around the globe, the work environment is dynamic, meaningful and fast paced.
 
what you will be doing:
work closely with the architecture and different software design teams.
implement new features in the core of nvidia nic firmware.
implement verifiers for advanced features in our advanced random firmware testing environment.
gain a deep understanding of system debug, networking technology and stacks, as well as the hw/fw/sw relationship.
you will learn how a big software project is operated, maintained, qualified and released, and how hardware and firmware are developed.

our networking product engineering team is looking for a TEST development engineer. the position combines an understanding of hw and sw to provide stable, efficient, smoothly running production tests, to enable high availability, while ensuring the quality of the products being shipped to customers.
what youll be doing:
design and develop automated tests for networking switches while working closely with the hw, asic, and sw engineering teams to achieve a reliable TEST with high coverage
exposed to various aspects of design, dft, and TEST of nvidia's next-generation network products
take a significant part in the definition and development of tests from the development level to the final TEST of network-systems
working with overseas manufacturing teams to increase yields, TEST coverage, and capacity, and reduce production costs

you will be part of rem department. road experience management (rem) is an end-to-end mapping and localization engine. its being used for full autonomy capabilities and services, generating validation processes and methodologies for such a technology giant is challenging, sufficient. since we are dealing with a complex system based on Machine Learning and image processing, the analysis and validation processes require deep thinking as well as advanced technical and analytic abilities. our analysts are responsible for running the analysis process and for providing deep analysis reports based on effective analysis of Big Data. what will your job look like:
lead and hands-on drive the teams transition toward extensive and effective use of automation, including implementing automated solutions, improving existing workflows, and actively supporting the team in adopting automation as part of daily development and testing activities
manage and oversee both automated and manual validation processes, ensuring thorough data review and quality control.
prepare clear, structured reports summarizing validation results, issues, and recommendations for technical and management stakeholders.
plan, track, and coordinate validation projects, maintaining schedules, identifying risks, and communicating progress across departments.
collaborate with algorithm developers, engineers, and other stakeholders to troubleshoot issues and propose improvements.
participate in the planning and design of advanced validation processes.

mentor new team members and enable existing team members to thrive.
support new ai fabric technologies based on nvidia networking solutions.
gain our customers trust, understand their needs, and translate them into technical actions and priorities.
work closely with multiple r&d teams from broad disciplines.
drive cooperation and alignment between ae, r&d, sales, business, and operations.
solve complex, highly visible customer issues across hw, fw, system and lead them to closure.
provide clear, constructive feedback to engineering and product/marketing on product requirements and quality.
own and improve methodologies, best practices, and debug flows used across the team.

leading the development of groundbreaking microelectronics packaging for networking business unit's future products
collaborating with world-leading vendors to develop highly ambitious packaging solutions
thriving in a dynamic and challenging environment