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Location: Caesarea
Job Type: Full Time and Hybrid work
Come join us and help shape groundbreaking solutions by designing, developing, and testing some of the most complex ASICs in the industry.
In this role, you will be part of the Switch ASIC Post-Silicon Electrical Validation (EPSV) team.
Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.
Handle all chip validation aspects, including:
Building validation plans.
Performing EPSV using advanced test and measurement equipment.
Writing tests in Python over device SDK.
Executing tests and analyzing results.
You will gain in-depth knowledge of chip architecture, functionality, and operating modes, enabling you to debug and resolve electrical chip-related issues.
Requirements:
Bachelors degree in Electrical or Computer Engineering.
At least 3 years of experience in hardware or post-silicon validation.
Hands-on experience with lab equipment performing high-speed, clock, and precise voltage measurements.
Knowledge of high-speed interfaces and high-power DC/DC design.
Preferred Qualifications
Experience bringing up ASICs on EVBs with Board Design, FPGA, SerDes, and Software teams.
Proficiency in debugging issues in the lab using VNA/TDR, oscilloscopes, and phase noise analyzers.
Experience developing testing environments, performing validation activities, and analyzing data.
Familiarity with production testing and yield improvement.
This position is open to all candidates.
 
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Location: Caesarea
Job Type: Full Time
Come join us and help shape groundbreaking solutions by designing, developing, and testing some of the most complex ASICs in the industry.
What You Will Do:
In this role, you will be part of the Switch ASIC Post-Silicon Electrical Validation (EPSV) team.
Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.
Handle all chip validation aspects, including:
Building validation plans.
Performing EPSV using advanced test and measurement equipment.
Writing tests in Python over device SDK.
Executing tests and analyzing results.
You will gain in-depth knowledge of chip architecture, functionality, and operating modes, enabling you to debug and resolve electrical chip-related issues.
Requirements:
Bachelors degree in Electrical or Computer Engineering.
At least 3 years of experience in hardware or post-silicon validation.
Hands-on experience with lab equipment performing high-speed, clock, and precise voltage measurements.
Knowledge of high-speed interfaces and high-power DC/DC design.
Preferred Qualifications
Experience bringing up ASICs on EVBs with Board Design, FPGA, SerDes, and Software teams.
Proficiency in debugging issues in the lab using VNA/TDR, oscilloscopes, and phase noise analyzers.
Experience developing testing environments, performing validation activities, and analyzing data.
Familiarity with production testing and yield improvement.
This position is open to all candidates.
 
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Location: Caesarea
Job Type: Full Time
Our Board Design Team is growing! Youll collaborate with top industry engineers within the fast-growing Cisco Silicon One group worldwide.
You will be part of a team driving our groundbreaking next-generation network devices-Cisco Silicon One. Our team operates in a startup-like atmosphere within a global, leading corporation.
Our design center is unique, hosting all silicon hardware and software development fields under one roof. Our Networking Chips deliver high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility. They are strategically placed in critical AI infrastructure, powering next-generation network devices and supporting advanced AI workloads. They deliver high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility.
Your Impact:
Spearhead innovative silicon architecture for AI infrastructure, guiding board design from concept through to mass production.
Act as the technical decision-maker for the project and collaborate with cross-functional teams in mechanics, thermal, PCB layout, and software/RTL.
Define product specifications, develop electrical schematics, and guide component selection.
Conduct hands-on testing in a lab environment and drive the PCB bring-up, characterization, and debugging stages.
Requirements:
B.Sc. in Electrical Engineering or equivalent practical experience.
3+ years of experience as a hardware/board design engineer, with a strong background in executing complex hardware projects.
Experience in high-speed and multi-layer PCB design.
Hardware-oriented, with experience in measurements, characterization, and using lab equipment and hands-on experience in PCB bring-up and systematic debugging.
Preferred Qualifications:
Demonstrated success in leading multi-disciplinary projects.
Strong project management abilities, self-driven, with excellent interpersonal skills.
System orientation with a multi-disciplinary approach and multitasking capabilities.
This position is open to all candidates.
 
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Location: Caesarea
Job Type: Full Time and Hybrid work
Youll be joining the post silicon validation team in PHY system group as part of the silicon development .
Our team deals with PHY and system aspects of the SerDes communication IP: PHY FW, calibrations, system definitions and operations and post-silicon validation including developing the automation infrastructure and tools.
We use latest silicon technologies and processes to build the largest scale and most complex devices at the edge of feasibility.
Requirements:
B.Sc or M.Sc in Electrical Engineering, Computer Science, or equivalent
Experience in PHY/SerDes validation (high‑speed SerDes characterization, link stability, PVT corners) and/or other PHY layer of communication systems
Proven ability in system‑level debugging to isolate faults across HW/SW/Silicon
Strong scripting/programming skills in Python or C++
Practical experience with lab instrumentation: oscilloscopes, BERTs, spectrum analyzers
Preferred Qualifications
Knowledge of signal processing / communication theory (DSP, modulation, link‑layer communication)
Linux proficiency, Git, and experience with Jenkins/DevOps automation frameworks
GUI development experience and database familiarity
Understanding of PCIe and Ethernet standards
System orientation with a multi‑disciplinary approach and strong multitasking capability
This position is open to all candidates.
 
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29/07/2026
Location: Caesarea
Job Type: Full Time and Temporary
Required Senior R&D System Application Engineer (12 Months Contract)
Innovation starts from the heart. We put patients first. We invest a significant proportion of our revenue towards research and development to drive and develop groundbreaking medical innovations for structural heart disease. As part of our R&D Engineering team, you will work closely with our Quality and Manufacturing teams to develop the latest tools and technologies to address significant, unmet clinical needs that impact patients lives around the world.
What will you do?
You will be part of an R&D team responsible for the development, integration, and validation of medical device systems. With a strong emphasis on hands-on development, data-driven engineering, with a problem-solving mindset. you will contribute to the full product development lifecycle - from the need, through signal processing and GUI development to system testing and clinical application. This role is designed for engineers who are passionate about building and refining medical device technologies in a multidisciplinary environment.
How youll make an impact:
Develop and improve medical device features within the portfolio as part of a multidisciplinary R&D team that includes mechanical, hardware, and software engineers. Main activities include - procedure development, algorithm development, GUI design and implementation, scripting, test automation, data acquisition, and data analysis and visualization.
Participate in the design and development of system-level features, supporting architecture decisions and translating clinical and functional requirements into working solutions.
Perform hands-on testing of medical device systems (implant systems, hardware, and software), including functional, integration, and exploratory testing to validate design performance and clinical readiness.
Lead test design efforts, including writing test cases, test procedures, and test reports. Collect, analyse, and summarize test data to support design decisions and issue investigations.
Execute and support test protocols in lab and simulated clinical environments. Accurately document results, observations, and issues to ensure traceability and compliance.
Collaborate with stakeholders and colleagues - including caregivers, R&D engineers, clinical specialists, marketing, and quality teams - to understand system behaviour, clinical workflows, and end-user needs, ensuring that developed solutions align with real-world application requirements.
Requirements:
What you'll need (Required):
Degree in an engineering discipline. Biomedical, Electrical, Software or Computer Science, Math, Information Systems, or a related area preferred.
Bachelor's degree + minimum of 3 years of experience in R&D roles.
Familiarity with medical devices, clinical systems, and product development processes.
Advantage - programming experience (Python, C++, LabVIEW, similar); experience with GUI development frameworks and algorithm design is a plus.
Solid technical aptitude with the ability to understand system-level designs, software development lifecycle, and associated challenges and risks; ability to work closely with engineers across disciplines.
What Else we look for (Advantage):
Strong analytical thinking and problem-solving skills with a development-oriented mindset.
Experience or strong interest in algorithm development, data processing, and GUI-based application development.
Ability to work collaboratively in cross-functional R&D teams and contribute across the development lifecycle - from concept through verification.
Hands-on, detail-oriented approach with a strong willingness to learn and adapt.
Ability to follow procedures accurately and document work clearly.
Comfortable working in lab environments and handling biological materials and technical equipment.
Clear written and verbal communication skills in English.
This position is open to all candidates.
 
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חברה חסויה
Location: Tel Aviv-Yafo and Caesarea
Job Type: Full Time and Hybrid work
we are looking for a IC Package Design Engineer.
In this role, you will contribute to the development of complex ASIC package designs from early planning and exploration through implementation and tapeout. You will collaborate across package design, layout, SI/PI, and silicon teams to help deliver high‑speed, robust, and manufacturable package solutions.
You will participate in package architecture activities, design tradeoff discussions, and technical problem solving while growing your expertise in advanced packaging technologies and system-level integration. This role provides an opportunity to work on some of the most advanced networking silicon products in the industry within a highly collaborative engineering environment.
Responsibilities:
As a member of the Package Design team, you will:
Lead the package design activities including planning, floorplanning, pinout optimization, stack‑up definition, and high‑speed routing suport.
Collaborate with SI/PI, silicon floorplanning, layout, and manufacturing teams to ensure high‑quality package solutions.
Support package implementation activities and work closely with layout designers to ensure alignment between design intent and physical implementation.
Participate in technical investigations, design reviews, and tradeoff discussions involving performance, manufacturability, and schedule considerations.
Assist in developing and improving package design methodologies, flows, and best practices.
Contribute to debugging, issue resolution, and package bring‑up activities as needed.
Requirements:
Bachelors degree in Electrical Engineering or a related field.
5+ years of experience in package, PCB, or high‑speed design engineering.
Strong understanding of high-speed signal design and power distribution networks (PDN).
Familiarity with industry-standard EDA tools for layout and design.
Strong communication skills with the ability to collaborate and coordinate effectively with cross-functional teams
Preferred Qualifications:
Masters degree in Electrical Engineering
Experience with advanced packaging technologies, interposers, or multi‑die systems
Knowledge of silicon floor planning, signal integrity (SI), and power integrity (PI) considerations
Proven track record to drive design improvements and lead stakeholder coordination throughout the design process
This position is open to all candidates.
 
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חברה חסויה
Location: Tel Aviv-Yafo and Caesarea
Job Type: Full Time and Hybrid work
Join the Front-End Design team, at the core of silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
Your Impact:
Review micro-architecture specifications
Implement Verification environment UVM based
Collaborate with Design engineers to resolve bugs and achieve coverage closure
Work with the firmware/Lab teams to verify chip flows
Perform debug, root-cause analysis, and post-silicon validation in the lab
Requirements:
B.Sc./M.Sc. in Electrical Engineering from a top university
4+ years of experience in the filed
knowledge with UVM and functional verification methodologies
Preferred Qualifications
Experience with MATLAB simulations and bit-exact modeling environments
Familiarity with mixed-signal systems and environments
Knowledge and hands-on experience with Clock Domain Crossing (CDC)
This position is open to all candidates.
 
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Location: Caesarea
Job Type: Full Time and Hybrid work
we are looking for a Junior Hardware Engineer - Signal & Power Integrity.
You'll be joining our Signal & power Integrity team, which is at the center of the silicon development .
Our SIPI engineers deal with all system development aspects and deliver detailed specifications to other development team.
As SIPI engineer youll be required to design and analyze high speed analog/digital signals for networking products, with emphasis on high speed signal and power analysis of ASIC, Package and PCB. Model/simulate/characterize high speed systems, including high speed I/Os, chip packages, printed circuit boards, and system interconnects. Overcome the challenges of ultra-high data rate and cutting-edge technology. We use the latest silicon technologies and processes to build largest scale and most complex devices at the edge of feasibility.
Requirements:
B.Sc or M.Sc Electrical Engineer graduate from leading Israeli Universities with average grades above 85.
Physics background.
Brilliant ambitious and motivated individual, regardless of previous experience.
Team players who enjoy big challenges.
People who can quickly ramp on multiple, interdisciplinary domains.
Preferred Qualifications:
Experience in ASIC package design, including optimizing pinouts, stack-ups, and high-speed routing.
Knowledge of silicon floor planning, signal integrity (SI), and power integrity (PI) considerations.
Hands-on experience with advanced testing and measurement equipment, including oscilloscopes and TDR/VNA analyzers.
Strong understanding of high-speed signal design and power distribution networks (PDN).
Experience in package design.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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חברה חסויה
Location: Caesarea
Job Type: Full Time and Hybrid work
we are seeking a Physical Design Engineer.
Meet the Team:
The Physical Design team owns backend methodology and flow development from RTL to GDS. The team plays a critical role in developing high-quality VLSI designs for some of most advanced silicon products.
We work with the latest silicon technologies and processes to build large-scale, complex devices that push the boundaries of feasibility. You will collaborate with experienced engineers across architecture, design, verification, and implementation to deliver high-performance silicon.
Your Impact:
You will be part of the team, which is at the heart of software and ASIC design efforts. As a Physical Design Engineer, you will contribute to backend implementation work across key stages of chip design, helping move complex designs from RTL toward GDS.
You will work on physical synthesis, place and route, optimization, timing closure, and floor planning activities. Success in this role means delivering high-quality implementation results, learning quickly from senior engineers, and helping improve the flow and methodology used by the team.
Requirements:
B.Sc. or M.Sc. in Electrical Engineering or a related field.
2+ years of hands-on experience in VLSI backend design or a relevant physical design domain.
Strong understanding of the Place & Route flow.
Hands-on experience with physical synthesis, place and route, optimization, timing closure, or design floor planning.
Preferred Qualifications:
Understanding of physical construction and integration concepts across backend implementation.
Knowledge of physical design verification methodology, including LVS and DRC.
Familiarity with physical design EDA tools such as Synopsys, Cadence, or similar platforms.
Ability to learn independently, take ownership of assigned tasks, and work effectively with teammates.
Strong problem-solving skills and attention to detail in complex technical environments.
This position is open to all candidates.
 
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Location: Caesarea
Job Type: Full Time
We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.

Responsibilities:
Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.
Requirements:
Requirements
Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience.
2+ years in design verification, with strong SV/UVM proficiency (Less experienced engineers with high university grades or vast knowledge in RTL design will also be considered)
Self-motivated, ability to work, lead and drive tasks to completion.
Great interpersonal skills.
Understanding of digital ASIC design flows and SoC development methodologies. experience with SoC/full-chip verification, simulation/debug tools, and Unix/Linux environments, scripting languages (Python, etc.) and version control.

Advantages
Knowledge in Low Power techniques and UPF standard.
Knowledge in Mix signals SoCs.
Experience with SW/HW Co-development
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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חברה חסויה
Location: Tel Aviv-Yafo and Caesarea
Job Type: Full Time and Hybrid work
we are looking for a Logic Design Engineer.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab
Requirements:
B.Sc./M.Sc. in Electrical Engineering from a top university
6+ years of experience in a relevant field
RTL design experience
Familiarity with UVM and functional verification methodologies
Preferred Qualifications:
Experience with MATLAB simulations and bit-exact modeling environments
Familiarity with mixed-signal systems and environments
Knowledge and hands-on experience with Clock Domain Crossing (CDC)
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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