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Location: Giv'atayim
Job Type: Full Time
We are looking for an experienced STA Lead Engineer to join our growing BE team. We are working on the most challenging and interesting ASIC chips. Come join us and have a big impact on our groundbreaking and innovative designs.
Responsibilities
Take part in STA activities for blocks, Sub Systems and Full chip, from definitions to TO
Analyze timing results, verify correctness and provide timing budget for the different partitions.
Own the timing constraints both for STA and P&R flow.
Working closely with architecture, design, PD and DFT teams to make sure timing closure and ensures product success
Identify risks and bottlenecks, work closely with PD, RTL and DFT teams, ensuring convergence throughout various project stages.
Participating in design methodology, reviews and tool automation work and definition
As part of this rule you will gain very good understanding of our HPC and AI designs and sub system as well as product targets.
Requirements:
BSc/MSc in Electrical Engineering/Computer Science.
8+ years of experience in VLSI backend (RTL2GDS).
5+ years experience in STA (Prime-Time/Signoff).
Experience Full chip STA on complex SoCs experience.
Expert knowledge and hands-on experience in timing closure & signoff methodologies.
Good knowledge of DFT architecture and DFT timing related issues
Good knowledge of Async timing concepts & verification.
Good knowledge of the full backend flows from RTL to TO. (Synthesis, FP, PnR , CTS , STA, EM/IR, Chip Integration, high-frequency designs).
This position is open to all candidates.
 
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29/12/2025
Location: Ramat Gan
Job Type: Full Time
Were building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems.
If youre driven by solving problems, some dont yet have names, this is where you want to be.
In this role, you will:
Establish and lead a Back-End team with emphasis on RTL to GDS flow, Floorplan, Synthesis, Place and route, clock-tree, STA, layout, signoff (Timing, DRC, LVS) and Power
Be responsible for the Backend execution and methodologies
Be responsible to guide and lead contractors
Requirements:
BSc. Degree in Electrical Engineering
At least 5 years experience as BackEnd engineer from a leading semiconductor company at advanced process technology
Proven leadership capabilities and experience
Hands-On experience in both Macro level and full-chip
Power and Noise analysis - Advantage
DFT knowledge - Advantage
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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29/12/2025
Location: Ramat Gan
Were building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems.
If youre driven by solving problems, some dont yet have names, this is where you want to be.
About The Position:
DFT (Design For Test) is a multidisciplinary field which involves many aspects of the chip design process, including: DFT architecture definition, RTL design, verification, backend implementation, STA, pre and post production activities and many more.
You will be part of a growing team that develops from scratch its DFT implementation flow and responsible for all DFT activities and you will closely work with multiple teams within the VLSI group.
Requirements:
Minimum of 5 years experience in the area of DFT
Knowledge of DFT concepts (MBIST insertion and Memory test validation/ Scan insertion, ATPG, coverage analysis)
Experience with Synopsys/Mentor tools and flow
Familiarity with logic design, verification and debug
Experience in scripting languages such as tcl, perl, shell, python, etc.
Experience with high speed interfaces (i.e. PCIe/USB) and/or DDR - an advantage
Excellent communication and team work skills and a very good English is required
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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29/12/2025
Location: Ramat Gan
Job Type: Full Time
Were building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems.
If youre driven by solving problems, some dont yet have names, this is where you want to be.
In this role, you will be:
Responsible for definition and micro-architecture of complicated digital blocks
Detailed documentation and RTL implementation including running EDA tools (Lint, CDC, simulation, debugging, synthesis and timing analysis)
Work closely with verification and architecture team
Participate in design methodology and tool automation work as needed
Requirements:
B.Sc. in Electrical Engineering
Minimum 2 years of experience in logic design from semiconductor companies
Knowledge and experience in Verilog and/or System Verilog
Knowledge of power management techniques for low power design
Familiarity with Clock domain crossing, simulation, debugging, synthesis and timing analysis
Knowledge in scripting languages such as Python or Perl - Advantage
Very good communication skills
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8477799
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Location: Tel Aviv-Yafo
Job Type: Full Time
We are driving innovation in automotive technology, developing solutions that power the next generation of vehicles. We are looking for a Junior Engineer who is eager to learn, grow, and make an impact in a dynamic and innovative environment. This is a unique opportunity to work alongside experienced professionals, gain hands-on experience, and contribute to projects at the forefront of automotive electronics. If you are passionate about technology, curious to explore new challenges, and excited to make a real difference, we are the place to develop your skills, innovate, and grow your career.
Why join us?
* Work on cutting-edge automotive projects.
* Learn from a talented and supportive team.
* Gain exposure to real-world automotive challenges.
* Grow your career in a collaborative and inspiring environment.
If youre ready to take the next step in your career and be part of something meaningful, wed love to meet you!
About The Position:
As a Junior ASIC Design Engineer, you will take part in the full lifecycle of advanced chips that power the next generation of vehicles. This is a hands-on, growth-oriented role where youll work closely with experienced ASIC engineers, gain exposure to real silicon, and build a strong foundation in chip design and verification. In this role, you will:
* Be part of a professional ASIC team working on cutting-edge automotive solutions.
* Support and learn from real emulation platforms used in production-grade designs.
* Contribute to RTL implementation and gain practical experience in design flows.
* Assist with verification and backend (BE) activities, learning industry best practices.
* Participate in silicon bring-up, seeing your work come to life on real hardware This position is ideal for curious engineers who want to learn fast, take ownership, and grow into a key contributor in the world of automotive semiconductor design.
Requirements:
* B.Sc. in Electrical Engineering (graduate with excellence or a 3rd-year student).
* Strong interest in ASIC / chip design and hardware development.
* Basic understanding of RTL design concepts - an advantage.
* Any exposure to programming or scripting (e.g., Python, TCL, PERL) - an advantage.
* Previous academic or practical experience in relevant fields - an advantage.
* Good English communication skills, both written and verbal.
* Team player with a positive attitude, curiosity, and willingness to learn.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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28/12/2025
Location: Herzliya
Job Type: Full Time
Power the Future with us! At SolarEdge (NASDAQ: SEDG), we're a global leader in smart energy technology, with over 3,000 employees, offices in 34 countries, and millions of installations worldwide. Our innovative solutions include solar inverters, battery storage, backup systems, EV charging, and AI-based energy management. We're committed to making clean, green energy the primary power source for homes, businesses, and beyond. With the growing demand for electricity, the need for smart, clean energy sources is constantly rising. SolarEdge offers amazing opportunities to develop your skills in a multidisciplinary environment, covering everything from research and development to production and customer supply. Work with talented colleagues, tackle exciting challenges, and help create a sustainable future in an industry that's always evolving and innovating. Join us and be part of a company that values creativity, agility, and impactful work. We are looking for a Senior ASIC Verification engineer with good grasp of the entire verification process – plan, execution and sign-off, excellent analytical skills, technical skills and high motivation to join our team and take part of the success. What you will be doing:
* Create a thorough verification plan out of IP specification and implement it to completeness.
* Build UVM-compliant IP verification environment from scratch.
* Debug to find root cause of issues.
* Full-chip verification from planning stage to tape-out, including gate-level testing.
* Testing using both System Verilog and C.
* Work in a diverse environment, collaborating with power engineers, communication experts and SW developers

Country:
Israel

City:
Herzliya
Requirements:
* B.Sc. in Electrical Engineering from a leading university.
* Over 5 years of experience in complex ASIC verification.
* Experience in building IP verification environment.
* Experience in UVM methodology.
* Good knowledge in Verilog.
* Experience in embedded C programming – advantage.
* Good communication and interpersonal skills. SolarEdge recognizes its talented and diverse workforce as a key competitive advantage. Our business success is a reflection of the quality and skill of our people. SolarEdge is committed to seeking out and retaining the finest human talent to ensure top business growth and performance
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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25/12/2025
Location: Herzliya
Job Type: Full Time
Our Chip Design team is growing! Join our high-end product design team and help shape the next generation of advanced semiconductor solutions. About us our company  has been delivering tens of millions of chips annually to leading tier-1 customers in the Security, Cloud, and Computing domains. We specialize in semi-custom, high-quality solutions, going above and beyond to meet our customers needs. Our Israel Design Center is fully self-contained, covering everything from product definition and architecture to design, software, validation, and TEST - meaning real ownership and no daily late-night calls across time zones We also pride ourselves on a warm, open culture where everyone knows each other, and every engineer can clearly see the impact of their work on the final silicon. We are looking for experienced Chip Design Engineers to join our team and take a key role in RTL design, new IP development, and SOC integration As part of the design team, you will be deeply involved in architectural exploration, protocol evaluation, and hands-on design work across multiple chip blocks. Responsibilities
* RTL design and implementation of new IPs
*  SOC integration and design ownership of chip subsystems
* Exploration and evaluation of new protocols and architectural solutions
* Close collaboration with architecture, verification, validation, software, and back-end teams
* Delivering high-quality, best-in-class RTL that meets performance, power, and area goals Why Join Us?
* Work on cutting-edge, high-volume silicon products
* Real impact on end-to-end chip development
* Collaborative environment with strong technical ownership
* A stable yet agile organization with a human, people-first culture
Requirements:
BSc or MSc degree in electrical / computer engineering from leading institutions 3-7 years of hands-on experience in VLSI / chip design Familiarity with the RTL-to-GDSII full flow - advantage Strong analytical thinking, communication skills, and ability to work in a multi-disciplinary team
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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23/12/2025
Location: Caesarea
Job Type: Full Time
We are looking for a hands-on, experienced Physical Design Engineer to join us and help define and implement next-generation AI SoC in an advanced technology node

You will play a key role in building and leading our physical design team, developing flows and methodologies, and driving the full RTL-to-GDSII implementation and signoff for one of the most advanced SoCs in the industry.

What Youll Do

Take part in shaping methodology and best practices in advanced technologies

Drive end-to-end implementation: synthesis, P&R, timing closure, and signoff

Collaborate closely with architecture and design teams on timing, floorplaning, partitioning, and power specification

Define and optimize static timing constraints, area, and power goals at block and top levels

Take part in flow development and automation to improve efficiency and quality of results
Requirements:
At least 3+ years experience with RTL2GDS flow

BSC/MSC in Electrical/Computer engineering

Deep understanding on STA principals, synthesis, and P&R flow

Solid experience in physical verification and advanced process nodes
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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23/12/2025
Location: Caesarea
Job Type: Full Time
Our group is responsible for the development of next generation SoC for AI Networking Compute . The development starts from product definition through architecture, design, verification and up to implementation.

The complex SoC is a high-performance device running AI scale-out for inference workloads computer for vision and audio processing, with technologies from multi-disciplines.
Requirements:
7+ years of experience as a VLSI design engineer
B.Sc./M.Sc. degree in electrical/computer engineering from a leading university
Experience in defining uarch and design of complex design units.
SoC design experience.
full cluster/block uarch, design, inital synth, lint, integrating and supporting PD, DFT and verification.
Experience in HW implementation of packet processing / Ethernet / Infiniband / RDMA Experience in high-speed interfaces DDR/PCIe
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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23/12/2025
Location: Caesarea
Job Type: Full Time
We are looking for a Senior Verification Engineer to be a significant part in developing a complex and innovative SoC chip in a start-up company.

Taking full ownership of entire domain, defining the verification strategy, writing, and executing verification plan in system Verilog UVM.
Requirements:
5+ years of experience as a Verification Engineer.
B.Sc./M.Sc. in Electrical/Computer Engineering from a leading university.
Strong knowledge of System Verilog and UVM methodology.
Experience in pre-silicon functional unit level/cluster/full chip verification.
Experience in verification of packet processing/Ethernet/RDMA/InfiniBand
Familiarity with SoC architecture, CPU subsystems, and multi-core designs.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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22/12/2025
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
we are seeking a motivated and detail-oriented Software Engineer to join our innovative VLSI Design Automation team. This group is responsible for building advanced VLSI CAD solutions and web-based platforms. We are looking for a full-stack engineer who is excited about handling large-scale data, enhancing web performance, and developing intuitive dashboards and applications. The ideal candidate brings solid backend experience, a strong data-driven mindset, a passion for learning, and excellent collaboration skills.
What youll be doing:
Design, develop, test, integrate CI/CD pipelines, deploy, and support features for web applications and dashboards.
Own the services and databases you build.
Identify areas for improving performance and inserting automation.
Requirements:
Bachelors degree in Computer Science or equivalent practical experience.
3+ years of hands-on full-stack development experience.
Strong proficiency in Python.
Experience working with database systems, including SQL (such as PostgreSQL or MySQL) and NoSQL solutions.
Hands-on experience with FastAPI.
Familiarity with CI/CD methodologies and related tools.
Experience building data visualizations in Python.
Strong working knowledge of Linux environments.
Ways to stand out from the crowd:
Background with Kubernetes and Docker.
Experience working with Kafka and event-driven architectures.
Experience with React, experience with logging and monitoring systems.
Background with data analysis libraries such as pandas and NumPy.
Previous exposure to machine learning concepts and frameworks.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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21/12/2025
Location: Yokne`am
Job Type: Full Time
Do you want to take part in accelerating the networking solution across our company's product portfolio? our company Co-packaged silicon-photonics group is seeking a dedicated R&D engineer to join our lasers and silicon-photonics validation team. We are seeking a skilled and experienced lasers and electro-optics engineer or physicist to join our team. The ideal candidate will have deep understanding of optics, lasers, and fiber-optic technology, together with expertise in laser testing, characterization, and packaging.
In this role you will participate in laser development for different networking products, including test setup design and test automation, perform tests and characterization of packaged lasers and of optical modules in a system. You will collaborate with cross-functional teams (R&D, verification, architects, FW, electronics, mechanics) internally and externally. This role requires hands-on experience and a deep understanding of optics and laser physics, high-speed testing, excellent Integration, problem-solving skills, and strong communication abilities.
What youll be doing:
Develop, implement and automate testing methodologies and procedures for laser characterization and performance evaluation , including power, wavelength, modulation, and noise measurements.
Document experimental results accurately and clearly present findings.
You will lead the design of verification setups for bringing up and testing the new SiPh transceiver chips.
Develop and implement laser testing methodologies and procedures to perform laser testing and characterization, including modulation and noise measurements.
Provide technical support and assistance to manufacturers of silicon photonics testing platforms.
Troubleshoot and diagnose technical issues related to equipment, processes, and software.
Document experimental procedures, results, and findings accurately and comprehensively.
Collaborate with cross-functional teams, including engineering, product development, and manufacturing, to resolve complex technical issues and implement system upgrades or modifications.
Requirements:
BSc. Degree (MSc. or PhD an advantage) in Electrical Engineering or Physics or related fields, with more than 5 years of experience.
5+ years of relevant experience in both laser testing and in high-speed electro-optical testing.
Proven experience working in an optics and laser laboratory, preferably in a research or development environment.
Strong problem-solving, debugging, and analysis with examples to prove it.
Experience with establishing complex optical lab setups. Proficient in using various electro-optical & electrical measurement tools.
Strong collaborative and interpersonal skills, with an ability to successfully guide and influence.
Ability to manage multiple tasks and priorities simultaneously, and work independently and demonstrate a high level of initiative and self-motivation.
Ways to stand out from the crowd:
Strong knowledge of laser diode physics, fiber optic technology, and silicon photonics technology and devices.
Experience with high-speed signal measurement of electro-optical devices.
Knowledge of programming languages, such as MATLAB, Python, or LabVIEW, for data analysis and automation.
Post-silicon validation and/or customer on-site debug/FA.
This position is open to all candidates.
 
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