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Required Electrostatic Discharge Engineer
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Electrostatic Discharge (ESD) Engineer, you will be responsible for designing, implementing and maintaining measures to prevent and control electrostatic discharge from electronic components and devices. The role involves analyzing, evaluating and mitigating potential ESD-related on die risks for advanced silicon technologies.
Responsibilities
Develop and implement ESD control plans and procedures for new silicon products.
Evaluate ESD risks associated with different stages of product design, manufacturing and handling, and recommend mitigation strategies to ensure compliance with industry standards.
Manage simulation tools such as: PERC (mentor), path finder (ansys).
Know ESD design rules and industry standards.
Collaborate with cross-functional teams to identify and resolve ESD-related issues in products and processes.

we are looking for a Senior Machine Learning Engineer to work on LLM-based systems with a strong emphasis on integration, end-to-end workflows, and production readiness. This role combines performance optimization (prefill/decode, throughput, latency) with hands-on work integrating components across the AI platform.
A significant part of the role involves building end-to-end integration flows and tests, particularly around token generation pipelines and system orchestration, as well as contributing to intelligent system behavior such as hardware selection and execution strategies. The role also includes developing system-level logic in Python for multi-tenant management, caching strategies, and service lifecycle management across the platform.
***This is not a Data Science position***
Responsibilities:
Build and maintain end-to-end integration flows across the AI inference pipeline (serving, orchestration, APIs, and infrastructure)
Design, implement, and optimize LLM inference workflows, including prefill and decode stages
Improve system performance with focus on throughput, latency, and interactivity
Write production-grade components in Python and integrate them into the broader system
Contribute to system-level logic such as smart hardware selection and execution strategies
Integrate models (open source and custom), services, and APIs into cohesive, reliable end-to-end application pipelines

Required Design Verification IP Lead, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of an edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive the distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Lead the verification of an edge AI IP, to be used in our edge-AI products.
Lead a team of chip verification engineers. Plan tasks, allocate people, hold verification design/code reviews, and drive verification execution.
Plan the verification of digital design blocks, including writing test plans, and other verification documents.
Code development of verification features and capabilities, and participate in RTL debug.
Work closely with Architecture, Software, Design, and Physical Design stakeholders to make technical decisions and represent project status throughout the development process.

We are looking for a Senior Software Engineer to help build and optimize large-scale, high-performance GenAI infrastructure and inference systems on Kubernetes.
As AI workloads increasingly move toward Kubernetes-native infrastructure, we are building systems that support distributed inference, performance optimization, reliability, observability, and production-grade deployment at scale.
This role is ideal for an engineer who can reason deeply about systems, performance, tradeoffs, and reliability, and who is comfortable owning difficult technical decisions end-to-end.
You will work across inference serving, distributed systems, optimization, and Kubernetes-native AI infrastructure.
What Youll Do:
Build and optimize high-performance Kubernetes-native GenAI inference systems
Work with modern inference stacks such as vLLM, SGLang, TensorRT-LLM, and related tooling
Work with Kubernetes-native distributed LLM inference frameworks such as llm-d and NVIDIA Dynamo
Design and implement optimization algorithms and performance improvements
Improve reliability, observability, deployment, and operational maturity of AI systems
Make architectural decisions and take ownership of technical outcomes
Collaborate with a small, senior engineering team focused on performance and production quality

Required Senior Post Silicon Validation Engineer, Networking
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Analyze the architecture and microarchitecture of complex hardware units and features, such as packet processing pipelines and advanced networking capabilities. Develop comprehensive post-silicon validation test plans based on a thorough understanding of the design and specifications.
Write, execute, and debug validation tests using Python or C/C++, running on pre-silicon emulation platforms and primarily on the silicon. Lead the bring-up, troubleshooting, and debug efforts on silicon, identifying root causes of hardware and software issues.
Collaborate closely with Architects, Designers, and other teams to drive bug fixes and ensure feature functionality. Contribute to the development of test infrastructure and methodologies to improve validation efficiency and coverage.

Required Silicon Validation Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Haifa, Israel; Tel Aviv, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Define, develop and execute post-silicon validation content on both pre-silicon setups and real silicon platforms in the lab.
Drive silicon from being a chip towards becoming a product.
Debug and investigate issues along cross-functional teams such as Firmware (FW), Software (SW), Design, Design Verification (DV), Architecture and multiple production teams.
Provide a quality functional coverage for our designs.

we are seeking a Lead System Architect to join our system architecture team and help define the next generation of our AI-SuperNIC scale-out chip.
AI scale-out communication is a critical element in modern data centers, and emerging standards such as Ultra Ethernet aim to address this challenge. This role focuses on defining a high-performance Smart NIC architecture optimized for GPU-centric AI workloads, with emphasis on low-latency, high-bandwidth data movement.
You will work across hardware and software domains, collaborating closely with AI, platform, driver, and VLSI teams to design a competitive scale-out networking solution.
Responsibilities:
Lead the software architecture and technical roadmap for or next-generation ultra low-latency AI-SuperNIC software stack, including drivers, firmware, libfabric, and libibverbs.
Define the partitioning and interfaces between hardware, firmware, kernel drivers, user-space libraries, and AI frameworks.
Lead the design and implementation of high-performance networking, RDMA, and GPU-direct communication capabilities.
Drive software support for emerging technologies and standards such as UEC, UALink, MRC and RoCEv2 ecosystems.
Work closely with hardware, system architecture, and VLSI teams to optimize performance, scalability, and feature delivery.
Define performance goals and lead profiling, benchmarking, and optimization efforts for GenAI and distributed AI workloads.
Collaborate with customers, partners, and open-source communities to ensure ecosystem compatibility and adoption.
Mentor software engineers and provide technical leadership across firmware, driver, and networking software development

Required SoC and IP Design Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use your ASIC design experience to be part of a team that develops the ASIC SoC from Plan of Record (POR) to Production. You will be creating SoC Level micro architecture definitions, Register-Transfer Level (RTL) coding and will do all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies. You will collaborate with members of architecture, software, verification, power, timing, synthesis design for test (dft) etc. You will face technical tests and develop/define design options for performance, power and area.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform RTL development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Participate in architecture feedback.

we are looking for a sharp, hands-on Product Manager to help define NR-NEXUS, our next-generation AI inference platform.
This role is ideal for experienced product manager who is fast-learning, technical, and ambitious. Youll work closely with Product, R&D, Marketing and customers engineering team to turn market needs, customer feedback, and AI infrastructure trends into clear product requirements, workflows, demos and PoCs.
What Youll Do:
Help define NR-NEXUS product capabilities, workflows, and use cases
Write clear PRDs, user stories, feature briefs, and competitive notes
Research AI infrastructure, SaaS platforms, model serving, and inference trends
Work with engineering to translate technical capabilities into product value
Support customer and partner discovery with sharp product thinking