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We are seeking a dynamic Field Service Engineer to join our team at our company, playing a critical role in advancing our renewable energy solutions. As a Field Service Engineer, you will contribute significantly to the future of various renewable energy products and solutions, serving as an interface between our customers and our company.


Ideal Candidate:
The ideal candidate will have a background as a practical Electrical Engineer or Electrical Engineer with a valid electrical license and comprehensive understanding of AC/DC, Low/Medium Voltage systems, networking and system controls. Proficiency in both Hebrew and English languages at a minimum of C1 level is required. The role will require on-call duty and the ability to oversee critical customer situations. Experience with Battery Storage solutions is highly beneficial, and a valid driving license is essential due to frequent travel requirements.


Responsibilities:
Serve as the primary interface between customers and our company, taking ownership of dispatched customer issues across various renewable energy solutions.
Provide comprehensive service and customer support during field visits or dispatches, running diagnosis on errors or technical problems.
Deliver on-site installation, repair, maintenance, testing tasks, upgrades, or rework activities for diverse renewable energy products.
Provide remote support to clients as needed.
Leading projects during commissioning and site acceptance services for various renewable energy solutions.
Adhere to operational procedures, processes, and practices consistently, ensuring compliance.
Follow applicable health and safety instructions and regulations for various renewable energy installations and services.
Maintain updated documentation, work instructions, and processes for existing and upcoming service contracts and agreements, including reports creation.

we ae seeking an experienced RF Systems Engineer to lead the RF domain within the hardware team, for the development of advanced communication systems.
This role includes full professional ownership of RF and antenna domains across the company-from architecture definition, through hands-on development and testing, to integration and technological leadership.
This is a key position with deep involvement in hands-on development, intended for an engineer with extensive practical experience, strong technical leadership skills, and attention to detail.
Job Description:
Professional leadership of the RF domain within the hardware team
Hands-on design and development of RF systems for advanced communication systems
Design, simulation, and optimization of antennas and antenna arrays
Definition of RF architecture and communication chains
Integration, calibration, RF testing, and hands-on troubleshooting in the lab
Daily work with advanced RF equipment, including measurements and performance analysis
End-to-end responsibility for RF system performance
Cross-functional work with hardware, software, mechanical, and algorithm teams
Technological leadership and professional support for development teams
Work with vendors and subcontractors in RF and antenna domains

we are seeking for an experienced Lead ATE Development Engineer to take ownership of the end-to-end design and implementation of test solutions for airborne systems and electronic assemblies. In this role, you will define the testing strategy, develop advanced test equipment, and integrate test capabilities across development, integration, and manufacturing processes.
Job Description:
Lead the design and development of Automated Test Equipment (ATE) for electronic boards, assemblies, and airborne systems.
Define test architectures, requirements, interfaces, and test coverage methodologies.
Design and integrate hardware, wiring, measurement equipment, simulators, and test software.
Develop engineering specifications, test procedures, operating instructions, and technical documentation.
Perform verification and validation activities, troubleshoot failures, and improve diagnostic capabilities.
Promote Design for Testability (DFT) practices in collaboration with hardware, software, and system engineering teams.
Support the transition of test systems from development to production and assist with qualification and acceptance testing.
Manage technical interactions with suppliers and subcontractors.

We are looking for a talented and experienced engineer to participate in the physical design of the companys product for leading one of our BE projects. This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on product architecture.

Responsibilities
Generate and analyze critical block- and chip-level static timing constraints
Spec and define full chip floor plan, including pin placement, partitions, and power grid.
Develop and validate high-performance, low-power clock network guidelines.
Perform critical block-level place and route and create designs that meet timing, area, and power constraints.
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations.
Work with vendors on defining physical design methodologies and assist in flow development for chip integration.

We are looking for a talented and experienced engineer to participate in designing the next era of computer architecture. In this position you will take part in designing the critical parts of our future chips. You will transform architectural requirements to micro-architectural specs, implement key blocks in RTL, and participate in post-silicon activities.

Responsibilities
Define and drive the design of advanced blocks from micro-architecture phase to netlist.
Support timing and constraints definitions work closely with the BE team on timing and physical implementation efforts.
Leading processes relating to power optimization.
Technology expert, building a knowledge base for the group.
Work with various teams to drive execution (SW, Architecture, verification, BE, etc).
Devise execution indicators and monitor and report execution progress to enable prioritization and clear decision making.

We are looking for an experienced, talented CPU ASIC front-end design expert and technical lead. In this role, you will take part in developing cutting-edge high performance best in class RISC-V CPU, from definition stage through planning stage and the development of new features while solving challenging implementation problems and ending in successful tape-out and product bring-up.

Responsibilities
Learn high performance RISC-V Arch and algorithms.
Define and drive the design of advanced and super complexed blocks from micro-architecture phase to tape out.
Work closely with various teams to drive execution (SW, Architecture, verification, BE, FPGA, postSi etc).
Devise execution indicators and monitor and report execution progress to enable prioritization and clear decision making.

Come help lead the design and development of one of the most ambitious products at the forefront of compute technology!

Responsibilities
Lead a physical design team responsible for all stages of the physical design process-floor planning, placement, clock tree synthesis, routing, timing, and power optimization at both block and subsystem levels.
Mentor and guide a team of physical design engineers through all stages of the design flow.
Collaborate closely with project managers and other technical leads to ensure timely delivery and successful completion of projects.
Drive the technical direction of the physical design process to ensure efficient, high-quality outcomes.
Develop and implement best practices for physical design and continuous improvements of design workflows.
Optimize designs for performance, power, and area (PPA) to meet project goals.
Ensure compliance with DRC (design rule checking) and LVS (layout versus schematic) requirements.
Drive timing analysis and closure, working closely with the RTL design team to resolve timing violations.

We are looking for a talented and experienced Physical Design lead to take part in the physical design and help lead the companys BE activities . This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on our final product.

Responsibilities
Lead blocks and sub systems execution from RTL to GDSII.
Clearly reflect status and execution metrics and help identify and solve execution bottlenecks.
Spec and define full floor plan, including pin placement, partitions, and power grid.
Develop and validate high-performance, low-power clock network guidelines.
Perform critical block-level place and route and create designs that meet PPA targets.
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations.
Work with vendors on defining physical design methodologies and assist in flow development for chip.

We are looking for a talented and experienced Logic Design Group Lead to drive and help our group to get to the next era of computer architecture. In this position, you will lead the architecture of our future chips, driving system-level understanding and the overall architectural flow. You will manage managers and technical leads while remaining highly hands-on, taking an active role in architectural decisions and technical execution across the system.

Responsibilities
Be accountable for your group's milestones & timelines
Leading your Group Architecture and developing their abilities
Technology expert, building a knowledge base for the group
Work with various teams to drive execution (SW, Architecture, verification, BE, etc)
Devise execution indicators, monitor and report execution progress to enable prioritization and clear decision-making
Acquire the system Architecture and be part of the leading technical FE forum

We are looking for a talented and experienced Logic Design Group Lead to drive and help our group to get to the next era of computer architecture. In this position, you will lead the architecture of our future chips, driving system-level understanding and the overall architectural flow. You will manage managers and technical leads while remaining highly hands-on, taking an active role in architectural decisions and technical execution across the system.

Responsibilities
Be accountable for your group's milestones & timelines.
Leading your Group Architecture and developing their abilities.
Technology expert, building a knowledge base for the group.
Work with various teams to drive execution (SW, Architecture, verification, BE, etc).
Devise execution indicators, monitor and report execution progress to enable prioritization and clear decision-making.
Acquire the system Architecture and be part of the leading technical FE forum.

We are looking for a talented and experienced engineer to take part in the Emulation and Prototyping efforts for the companys core product. This position involves building a complex emulation environment from scratch, and collaborating with software, design, and verification teams. In this role, you will be leading emulation from A to Z and will have a critical impact on the company.

Responsibilities
Develop and build complex emulation models for coming generations of our accelerators, including transactors like PCIe, SPI, and embedded CPUs.
Work with the software, design, development, and verification teams to understand the functional and performance goals of the products design.
Optimize the model for speed and capacity and develop debug abilities to support software and firmware teams.
Work with software design and development teams to define and develop BFM, test bench, and checker tools.
Review specifications and develop attributes, tests, and coverage plans for the emulation system.