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The HW Board Design team is at the heart of our hardware development lifecycle, ensuring that every design is robust, testable, and ready for high-volume production. We bridge the gap between initial architecture and final qualification, playing a critical role in delivering high-quality networking solutions that power the internet. Our team is a collaborative group of technical experts who thrive on solving complex signal and power integrity challenges in a fast-paced, innovative environment. Joining this team means working on cutting-edge technology where your leadership directly impacts the reliability of global systems. We value a proactive, team-oriented mindset and a passion for engineering excellence.

Your Impact:
You will be responsible for leading hardware board design activities with a strong focus on test, qualification, and readiness for production. This role spans all phases of hardware development, from architecture and design through bring-up, validation, and qualification, combining deep technical expertise with leadership and cross-functional coordination.

Lead and mentor the hardware engineering team focused on board design, test, and qualification.
Define hardware architecture and board-level design strategy with test, qualification, SI, and PI requirements in mind.
Oversee schematic design, PCB layout, and component selection.
Review designs for quality, reliability, cost, manufacturability, testability (DFM/DFT), signal integrity (SI), and power integrity (PI).
Own test readiness, including support for bring-up, debugging, validation, and qualification.
Manage schedules, task prioritization, and resource allocation.
Work closely with FW, SW, mechanical, QA, test, and manufacturing teams.
Drive design reviews, SI/PI risk analysis, and technical decision-making.
Support transition from prototype to qualified hardware and production release.
Ensure compliance with relevant standards and qualification requirements.

Your Impact:
Develop advanced verification environments using SystemVerilog and UVM.
Write, run, and debug testbenches to ensure complete functional coverage.
Drive pre-silicon and in-lab debug activities to resolve complex issues.
Collaborate with RTL, architecture, and physical design teams to achieve design closure.
Support methodology development, scripting, and automation to enhance productivity.
Contribute to the success of Cisco Silicon One, powering the next generation of Internet infrastructure.

Your Impact:
Write and review micro-architecture specifications.
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements.
Contribute to full chip integration, timing methodology, and analysis.
Collaborate with verification engineers to resolve bugs and achieve coverage closure.
Work with the physical design team to close timing and PnR issues.
Support design methodology evolution and best practices.
Perform debug, root-cause analysis, and post-silicon validation in the lab.

Join the PHY System team, part of our core silicon development group.
Our team is responsible for PHY and system-level aspects of some of the most advanced networking devices in the industry, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.

We work with the latest silicon technologies and processes to build large-scale, highly complex devices at the edge of feasibility. Youll be part of a unique design center that hosts all silicon HW and SW disciplines under one roof, operating in a startup-like environment within a stable, world-leading company.

We are transforming the industry with a unified, programmable silicon architecture that powers our future routing portfolio and helps shape the Internet for decades to come.

Your Impact:

Develop PHY firmware and system-level features for advanced networking ASICs.

Design and implement PHY calibrations and system definitions.

Participate in post-silicon validation, including lab bring-up, debugging, and performance analysis.

Collaborate closely with PHY, system, firmware, and silicon design teams.

Contribute to defining system operation modes and end-to-end device behavior.

Help drive the development of next-generation, high-scale networking solutions using cutting-edge silicon technologies.

What You'll Do:

You'll develop Core Software technologies at the heart of tomorrow's leading infrastructure solutions, tackling the entire range of challenges from user-facing API-s, through high-level algorithms, all the way down to firmware.

The team develops breakthrough next-generation silicon products.

If you're looking to work with outstanding people, developing the first iteration of world-class products, join us!

In this role, you will:

Design and develop data plan software driving the world's most sophisticated infrastructures, using a modern P4 which is a domain-specific language for network devices, specifying how data plane devices (switches, routers, filters, etc .) process packets.

Gain intimate knowledge of world-class silicon and programming models.

Work with architecture and design teams to define the next generation of ASIC products being developed.

Join the PHY system team, a pivotal part of our development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.

Key responsibilities include:

Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.

What Youll Do:

Youll be part of the group driving next-generation network devices within a startup-like atmosphere inside a well-established, leading corporation.

Our unique design center integrates all silicon hardware and software development disciplines under one roof. We are revolutionizing the industry by building a new internet for the 5G era, with a unified, programmable silicon architecture that will underpin Cisco's future routing products. Our devices are designed for adaptability across service providers and web-scale markets, delivering high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility.

Join the PHY system team, a pivotal part of our development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.

Key responsibilities include:

Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.

What Youll Do:

Youll be part of the group driving next-generation network devices within a startup-like atmosphere inside a well-established, leading corporation.

Our unique design center integrates all silicon hardware and software development disciplines under one roof. We are revolutionizing the industry by building a new internet for the 5G era, with a unified, programmable silicon architecture that will underpin our future routing products. Our devices are designed for adaptability across service providers and web-scale markets, delivering high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility.

We are seeking a CAD Engineer to join the Physical Design team.

You'll be joining our Physical Design team within us, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Your Impact:

Review micro-architecture specifications.

Supervise verification team members and provide professional guidance.

Implement Verification environment UVM based.

Collaborate with Design engineers to resolve bugs and achieve coverage closure.

Work with the firmware/Lab teams to verify chip flows.

Perform debug, root-cause analysis, and post-silicon validation in the lab.

As a key member of the team, you will be responsible for developing a state-of-the-art functional simulator for the family of devices. This simulator is a critical product that streamlines the development process and significantly reduces time-to-market.

In this role, you will:

Collaborate closely with the ASIC Architecture team to implement an accurate and efficient software model based on the architecture specifications.

Partner with both Software and Hardware design teams, providing support as they use the simulator as the golden reference for hardware implementation.

Ensure the simulator meets the highest standards of performance, reliability, and usability.

Contribute to defining best practices and methodologies for model development, validation, and integration. 

Physical Design team within us is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

Your Impact
You'll be part of the team, which is at the heart of our software and ASIC design efforts.

You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.