לוח משרות דרושים מהנדסים בחיפה וסביבתה

We are seeking a Senior software engineer (10+ years) with deep experience in backend engineering, scalable systems, and Real-Time environments. This is a high-ownership, end-to-end role with full responsibility for architecture and development of core systems. You will design and build distributed backend services, async pipelines, and low-latency systems, integrating AI model outputs into production-grade workflows. The role is primarily backend (~90%), with enough frontend capability (~10%) to independently ship simple UI components when needed.

Youll work hands-on, building modular, self-contained services and supporting Real-Time video pipelines. The role involves close collaboration with the CTO and research team, driving technical decisions, and owning system reliability end-to-end-from design and testing through deployment and production stability in real-world enviroments

Mechatronics & Components Engineer We are seeking a Mechatronics & Components Engineer to support the development of advanced products through selection, evaluation, and integration of mechanical and electromechanical components.

We are looking for an experienced Head of Process Engineering to lead our manufacturing processes during a critical growth phase.
This role includes end-to-end responsibility for process development, optimization, stabilization, and operational control, while building the process infrastructure needed to support production scale-up and long-term quality, consistency, and repeatability.
This is a highly Hands-on role, especially in the initial phase, with a strong focus on process improvement, troubleshooting, and operational stabilization. Full on-site presence in Caesarea is required due to the Hands-on nature of the role and the need for close involvement in process development, equipment oversight, production support, and cross-functional execution.
Key Responsibilities
Lead, develop, and optimize manufacturing processes across the company
Ensure process stability, repeatability, and scalability
Drive continuous improvement initiatives in early-stage production
Establish and implement process control methodologies
Identify and resolve process inefficiencies, deviations, and yield issues
Oversee machine operation, calibration, maintenance, and verification
Ensure proper documentation and compliance with equipment and operational procedures
Work closely with R&D on process development and transfer to production
Partner with QA to ensure process compliance, validation, and quality standards
Lead processes in an advanced manufacturing environment with a strong focus on precision, consistency, and control.

As a Wireless Design Verification Engineer, you will be part of a team that is responsible for pre-silicon RTL verification of communication subsystems, SoC sub-systems and chip-level functionality. The activity may focus on block level, sub-system level or chip level, including end-to-end simulations of the entire data/control path. You will interact with DV methodologists, designers and communication systems engineers to develop reusable testbench and verification environment deploying the latest methodology with metric driven verification.
Description
- Own critical block and sub-system verification of wireless SoC projects
- Architect and develop testbenches and environments, by using state-of-the-art verification methodologies
- Define verification plan, create, simulate and debug test scenarios
- Drive regression and coverage analysis to ensure high quality DV
- Collaborate with design and systems engineering teams to review requirements, specifications and architecture, extract features and define DV attribute

At High Sec Labs (HSL), a global leader in cybersecurity and secure connectivity solutions, we are looking for a talented Electronics Engineer to join our advanced development team. About the Role:
As part of our hardware group, you will take an active role in developing cutting-edge electronic products in the communication and cybersecurity domains. The role involves end-to-end board design, bring-up of new products, and integration of complex systems combining RF circuits, analog components, processors, and FPGAs.
Key Responsibilities: Design, bring-up, and validation of electronic boards and systems. Integration of RF, analog, digital, and FPGA-based circuits. Debugging, troubleshooting, and improving existing products. Close collaboration with multidisciplinary teams, including software and system engineers. Supporting the full product lifecycle from concept to production.

About Us: HSL (HighSecLabs) is a leading high-tech company specializing in cybersecurity and advanced technology solutions, including secure electronic enclosures and isolation systems for defense, government, and critical infrastructure. We pride ourselves on a professional, supportive, and growth-oriented work environment where employees can develop and thrive.
We are currently seeking a Senior Mechanical Designer for a full-time position. This is an excellent opportunity to lead complex projects from concept to mass production and make a real impact in a dynamic, innovative environment.
Responsibilities Develop and lead mechanical assemblies in collaboration with hardware engineers. Design structures and enclosures for products compliant with MIL-STD-810 (airborne and ground systems). Work with SOLIDWORKS and prepare detailed drawings of parts and assemblies. Support manufacturing and assembly processes, including work with suppliers in Israel and abroad. (Advantage) Thermal, cooling, and optical design of systems.

As a Design Verification Manager for the IP Group, you will lead a focused team responsible for the quality and reliability of our critical IP blocks. You will steer the IP verification roadmap, oversee the development of complex testbenches, and ensure our next-generation AI silicon meets the highest standards. Leading a team of talented engineers, you will tackle challenges at the unit and sub-system levels, playing a pivotal role in delivering high-performance hardware for the worlds largest AI clusters.

Key Responsibilities



Lead and mentor a team of design verification engineers, defining the technical roadmap and methodology for ASIC verification across unit and IP/sub-system levels
Drive the creation and execution of comprehensive design verification plans, ensuring all functional requirements are met on schedule for complex digital IPs
Oversee the architecture and maintenance of block-level verification strategies, heavily utilizing SV-UVM, alongside Formal Verification where applicable
Define functional coverage goals and quality metrics, driving the IP team toward 100% verification closure and sign-off
Partner closely with IP Design and Architecture teams to align on specifications, root-cause complex bugs, and optimize the IP development cycle

As an Expert EMIR & Power Integrity Lead, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will own from block level to full-chip the Electro-Migration and IR Drop (EMIR) methodology, analysis, and sign-off, working at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering.

You will be responsible for defining power grid architectures and validating that products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes. Your work will directly impact the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities

Lead static and dynamic IR drop analysis, signal/power electromigration (EM) verification, and self-heat analysis from block level to full-chip sign-off
Define and implement robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
Collaborate with Physical Design teams to define optimal power grid structures, via pillars, and strap distributions to minimize voltage drop while maximizing routing resources
Work closely with Analog/SerDes designers to analyze current profiles and ensure robust power delivery to sensitive high-speed IP blocks
Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis, optimizing bump patterns and package routing for superior Power Integrity
Drive root-cause analysis for voltage drop violations and EM risks; propose and implement layout fixes alongside the PD team
Verify current density rules for ESD protection networks and ensure compliance with foundry reliability constraints
Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data

we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters.

As an Expert IC Package Design Lead, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon.
You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners.You will be responsible for defining package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling products to operate reliably in the worlds most demanding AI and cloud environments.

Key Responsibilities

Own end-to-end IC package design, from early architecture and feasibility through detailed design, qualification, and high-volume manufacturing
Define package architecture and technology selection (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
Lead signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
Drive package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and mechanical constraints
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
Interface with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets
Lead package-related risk assessment, failure analysis, and corrective actions during bring-up and production ramp
Support NPI, qualification, and product sustainment activities, including vendor audits and technical reviews