לוח משרות דרושים ASIC / VLSI משרה מלאה

Requirements:
What we need to see:
B.Sc./M.Sc. in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
5+ years of experience in VLSI CAD tool development, with a strong focus on integrating AI/ML techniques into EDA workflows.
Proficiency in Python and at least one AI/ML framework (such as TensorFlow, PyTorch, or scikit-learn).
Hands-on experience with VLSI physical design and familiarity with industry-standard EDA tools (e.g., Synopsys, Cadence).
Knowledge of data preprocessing, feature engineering, and model deployment as applied to VLSI design challenges.
Experience developing and maintaining automation scripts (Python, Perl, Tcl, Make).
Strong analytical skills in evaluating the impact of AI solutions on design quality, performance, and productivity.
Excellent communication skills and the ability to work cross-functionally in a fast-paced environment.
Self-motivation, attention to detail, and a track record of delivering robust solutions to production.

Ways to stand out from the crowd:
Demonstrated experience deploying AI/ML models in production VLSI CAD environments.
Contributions to open-source AI/EDA projects or publications in relevant conferences/journals.
Deep understanding of VLSI design challenges-such as timing closure, power optimization, or yield enhancement-and how AI can address them.
Experience with cloud-based or distributed compute environments for large-scale AI training and inference.
Strong ownership, curiosity, and a passion for continuous learning and innovation.

Requirements:
B.Sc. in Electrical/Computer Engineering or equivalent.
5+ years of experience as a VLSI Verification Engineer.
Expertise in System-Verilog and UVM.
Strong software development skills and the ability to develop reusable verification components and utilities.
Strong organizational and planning skills, with the ability to prioritize and drive verification projects to completion.
Effective communicator with a structured, detail-oriented approach to problem-solving and collaboration.
Advantages:
Experience with Git, Python, code templating methods, and open-source verification workflows.
Familiarity with full-chip level aspects of VLSI verification (reset architecture and sequences, power domains and modes, etc.).
Experience in firmware verification, including emulation-based verification on FPGA.
Experience with formal verification or mixed-signal simulation.

Requirements:
8+ years of hands-on experience with ASIC physical design (RTL-to-GDS).
Proven experience taking multiple full-chip SoCs from RTL through tapeout.
Deep knowledge of Cadence and/or Synopsys backend flows (experience with both is a strong plus).
Strong understanding of PnR, timing closure, SI, power, DRC/LVS, and signoff.
Excellent debugging and problem-solving skills.
Strong scripting skills in TCL and Python.
Nice-to-have / Advantage:
Experience with multiple power domains and low-power design techniques.
Background that spans both frontend (RTL) and backend.
Experience influencing or defining methodology across teams or projects.
Personal skills

Innovation, quick learning abilities
Team player
Commitment, full ownership of tasks
Excellent communication and presentation skills
Customer orientation
A strong sense of ownership.

Requirements:
3-5 years of hands-on experience with ASIC physical design (RTL-to-GDS).
Proven experience taking multiple full-chip SoCs from RTL through tapeout.
Deep knowledge of Cadence and/or Synopsys backend flows (experience with both is a strong plus).
Strong understanding of PnR, timing closure, SI, power, DRC/LVS, and signoff.
Excellent debugging and problem-solving skills.
Strong scripting skills in TCL and Python.
Nice-to-have / Advantage:
Experience with multiple power domains and low-power design techniques.
Background that spans both frontend (RTL) and backend.
Experience influencing or defining methodology across teams or projects.
Personal skills:
Innovation, quick learning abilities
Team player
Commitment ,full ownership of tasks
Excellent communication and presentation skills
Customer orientation
A strong sense of ownership.

Requirements:
B.Sc. in Electrical Engineering
Experience in defining architectures DSP/CPU/GPU processor cores is an advantage
Experience in HW acceleration of AI
Architecture modeling experience is an advantage
System C knowledge is an advantage
10+ years in VLSI architecture and design (less can be accepted in case of a unique candidate)
Skills
Good interpersonal skills
Very good technical skills
Team player
Creative
Independent and self-learning.

Requirements:
BSc or MSc in Electrical Engineering or Computer Engineering.
8+ years experience in full chip design.
Experience in leading the full-chip level design and successfully taping out multiple intricate SoCs.
Experience in floor planning, integration, signoff methodologies, and signoff tools for hierarchical designs.
Experience with SoC design practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration.
Expert knowledge of the entire backend design flow from RTL to TO.
Experience with STA (Static Timing Analysis) tools like primetime or tempus.
Experience with IR drop tools like Ansys Redhawk or Volta's.
Physical Verification Expert (DRC/LVS).
Strong independent and motivated to learn quickly, hard-working, and is results oriented.
Good social skills and ability to work collaboratively with other teams.
Preferred
Experience with high-speed serial interfaces such as PCIe, DDR, Ethernet.
Familiarity with advanced DFT flows & tools.
Strong proficiency in scripting language, such as, Perl, Tcl, Python, Make, and automation methods/algorithms.

Requirements:
B.Sc. in Electrical Engineering or a related field.
6+ years of experience in ASIC/SoC Verification.
Experience leading verification planning and execution independently.
Preferred
Familiarity with RDMA, Ethernet, DDR or RISC-V.

Requirements:
BSc or MSc in Electrical Engineering or Computer Engineering
8+ years of VLSI experience.
Experience with multi clock domain, multi power domain designs (UPF).
Methodologic approach.
Strong Motivated to learn quickly, hard-working, and is results-oriented.
Great interpersonal relations skills.
Preferred
Networking design experience - Major Advantage
Backend experience: STA tools, formal equivalence tools, frontend/backend handoff methodologies.
SoC design/Integration experience.
Proven Methodologies and Environmental Building Experience.
Strong proficiency in scripting language, such as, Perl, Tcl, Python, Make, and automation methods/algorithms.

Requirements:
BSc or MSc in Electrical Engineering or Computer Engineering.
4-7 years of experience in FPGA prototyping or emulation of ASIC/SoC designs
Strong understanding of digital design and RTL (Verilog/SystemVerilog/VHDL).
Hands-on experience with at least one emulation/prototyping platform (Palladium, Protium, Veloce, ZeBu, or FPGA-based)
Good knowledge of synthesis, timing closure, and design partitioning for FPGA/emulation.
Familiarity with verification methodologies and environments (UVM/SystemVerilog/C).
Experience with scripting (TCL, Python, Perl, or Shell) for automation.
Strong problem-solving and debugging skills.
Ability to work in a fast-paced, collaborative environment.
Excellent communication and teamwork skills.
Preferred:
Exposure to software bring-up, driver validation, or firmware testing on emulation.
Knowledge of bus protocols (Ethernet, DDR, etc.).
Experience with debug tools (waveform viewers, logic analyzers, or emulation debug frameworks).
Background in SoC architecture and hardware/software co-design.

Requirements:
* A VLSI Design Engineer with extensive experience in backend design.
* B.Sc./M.Sc. in Electrical Engineering.
* Strong understanding of Place & Route flow.
* 7+ years of hands-on experience in a relevant domain
Preferred/Advantageous Qualifications:
* Deep understanding of all aspects of Physical construction and Integration.
* Knowledge in Physical Design Verification methodology LVS/DRC.
* Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
* Great teammate, self-learning skills, and ability to work autonomously.

Requirements:
B.Sc./M.Sc. in Electrical Engineering from a top university
​Minimum of 8 years of proven experience in a relevant field
RTL design experience
Familiarity with UVM and functional verification methodologies
Preferred Qualifications:
Experience with MATLAB simulations and bit-exact modeling environments
Familiarity with mixed-signal systems and environments
Knowledge and hands-on experience with Clock Domain Crossing (CDC)

Requirements:
A VLSI Design Engineer with extensive experience in backend design
B.Sc./M.Sc. in Electrical Engineering or Computer Engineering with relevent background.
​ 5+ years of hands-on experience in a relevant domain
Strong understanding of Place & Route flow
Preferred qualifications:
Deep understanding of Physical construction and Integration.
Knowledge of Physical Design Verification methods like LVS/DRC and formal verification.
Experience with PD CAD and Physical Design EDA tools (e.g., Synopsys, Cadence).
Ability to support technology adoption and new tool integration.
Great teammate, self-learner, and able to work independently

Requirements:
B.Sc./M.Sc. in Electrical Engineering from a top university
3+ years of experience in a relevant field
RTL design experience
Familiarity with UVM and functional verification methodologies
Preferred Qualifications:
Experience with MATLAB simulations and bit-exact modeling environments
Familiarity with mixed-signal systems and environments
Knowledge and hands-on experience with Clock Domain Crossing (CDC)

Requirements:
Bachelor's degree in Computer Science, Software Engineering, or related field
Minimum 7 years of software development experience, part of them as a manager of a development team
Proficiency in C++ and low-level programming
Demonstrated ability to design and implement complex software solutions
Proven track record of technical leadership
Preferred Qualifications:
Experience with ASIC and Network technologies
Background in large-scale distributed systems
Expertise in developing high-performance software that handles billions of packets
Advanced system design and architectural skills
Deep understanding of network state modeling and monitoring systems

Requirements:
B.Sc./M.Sc. in Electrical Engineering from a top university
RTL design experience
Familiarity with UVM and functional verification methodologies
Preferred Qualifications:
Experience with MATLAB simulations and bit-exact modeling environments
Familiarity with mixed-signal systems and environments
Knowledge and hands-on experience with Clock Domain Crossing (CDC)