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We are looking for a satellite networking Lab Coordinator. You will be responsible for overseeing our cutting-edge physical & virtual lab operations, ensuring smooth, automatic & reliable functionality, and driving innovation in our multidisciplinary technological solutions.

What you will do
Plan, organize, and oversee day-to-day operations of the lab to ensure efficiency and effectiveness.
Maintain and manage lab equipment, tools, and supplies, ensuring compliance with security standards.
Automate deployment, maintenance & monitoring processes, to support the R&D delivery processes.
Collaborate with R&D teams to plan, coordinate, and execute research initiatives and experiments within the lab.

Required Application Development Technical Lead
Reports to: Application Development Manager
Location: Afek Industrial Park, Rosh Haayin
What Will You Do?
Lead the system process development for new technologies in the textile printing industry (including new inks, workflows, and systems).
Develop applications and conduct experiments to test and refine innovations.
Plan and conduct experiments using existing systems and prototypes
Develop and deliver optimized solutions with clear performance status and measurable KPIs
Identify gaps in existing processes, propose, and define improvements. Map gaps, opportunities and suggest performance envelope improvements
Draft specifications (software and PRD), define project steps, procedures, and test plans.
Analyze, summarize and present multi component complex issues, using methodological troubleshooting skills.
Act as a bridge between R&D, marketing, and customer needs, becoming an expert in the application of technology to customer requirements.
Analyze complex, multi-component challenges and provide solutions.
Provide support to Customer Service and other Development departments as needed.
Independently manage projects and tasks from initiation to completion.

You'll be joining our Silicon One Signal & power Integrity team, which is at the center of the silicon development at Cisco. Our SIPI engineers deal with all system development aspects and deliver detailed specifications to other development team. As SIPI engineer youll be required to design and analyze high speed analog/digital signals for networking products, with emphasis on high speed signal and power analysis of ASIC, Package and PCB. Model/simulate/characterize high speed systems, including high speed I/Os, chip packages, printed circuit boards, and system interconnects. Overcome the challenges of ultra-high data rate and cutting-edge technology. We use the latest silicon technologies and processes to build largest scale and most complex devices at the edge of feasibility.

Our unique research team is expanding, we are looking for smart and humble team members to join the team and solve complex problems. Our technical challenges include developing new trading strategies, improving the performance of our algorithms, finding new ways to beat the markets.
As an ML researcher you will collaborate with our R&D team to execute live trading strategies.
If you are looking to make an impact by putting into practice successful ideas and seeing immediately the outcome, make influence on financial performance this is a great opportunity.
In this role you will:
Mange and lead independent research applying ML/DL methods to a wide variety of datasets.
Creatively find new trading strategies
Work with other team members to optimize Algorithms

testing electro-optical and electrical chips and systems.
link-level performance characterization, verification, and debugging.
responsibility for complicated setups establishments, covering both optical and electrical components
characterizing optical and electrical performance using lab equipment and sw tools.
take an active part in silicon bring-up while managing e2e testing of the newest asics, with the objective of driving product to mass production with first-in-class performance.
characterizing products performance using lab equipment, such as oscilloscope, spectrum/network analyzer, pattern-generator, etc.
working in front of various TEST teams, with the responsibility of addressing issues and monitoring the TEST flows conducted by them

as a quality and reliability (q&r) engineer, you will lead the qualification and long-term reliability of advanced system -on-chip ( SOC ) and RF semiconductor products for automotive applications. youll work across digital and RF domains to ensure robust performance and compliance with industry standards. what will your job look like:
define and manage quality and reliability specifications, simulations, and qualification plans for SOC and RF die and package.
plan and execute automotive-grade qualifications per standards such as aec-q100, jedec jesd22, and iatf 16949.
design and implement die-level and package-level stress tests.
select and prepare electrical, environmental, and mechanical TEST platforms for reliability testing.
define requirements for pre-si q&r (e.g. esd, lu, em, ir drop), design-for- TEST (dft), electrical characterization, and post-si q&r testing of digital, mixed-signal and RF socs.
collaborate extensively with internal design teams, external subcontractors, and outsourcing partners (osats).
lead failure analysis, reliability modeling, and corrective action processes (e.g., 8d, fmea, fmeda).
document and certify automotive standards compliance, including ppap/apqp deliverables.

as a quality and reliability (q&r) engineer, you will lead the qualification and long-term reliability of advanced system -on-chip ( SOC ) and RF semiconductor products for automotive applications. youll work across digital and RF domains to ensure robust performance and compliance with industry standards.
what will your job look like:
define and manage quality and reliability specifications, simulations, and qualification plans for SOC and RF die and package.
plan and execute automotive-grade qualifications per standards such as aec-q100, jedec jesd22, and iatf 16949.
design and implement die-level and package-level stress tests.
select and prepare electrical, environmental, and mechanical TEST platforms for reliability testing.
define requirements for pre-si q&r (e.g. esd, lu, em, ir drop), design-for- TEST (dft), electrical characterization, and post-si q&r testing of digital, mixed-signal and RF socs.
collaborate extensively with internal design teams, external subcontractors, and outsourcing partners (osats).
lead failure analysis, reliability modeling, and corrective action processes (e.g., 8d, fmea, fmeda).
document and certify automotive standards compliance, including ppap/apqp deliverables.

what youll be doing:
one responsibility of this position will be handling various types of testing of nvidia ics.
perform ic testing in order to produce reliable and precise data to support ic devices analysis.
maintaining and operating laboratory equipment such as ic evaluation systems, htol system, scopes, dvms and another tooling.
reading schematics of electronic circuits.
support all related activities such as iqc, oqc, ic inventory managing and shipments.
carrying out q&r tasks and following strict execution methodologies.
following and ensuring strict safety procedures and safety checks.

We are expanding our algorithm team working on operational defense command-and-control systems and are looking for a Senior Tracking and Data Fusion Algorithm Engineer. This role focuses on the development of real-time multi-target tracking and sensor fusion algorithms deployed in mission-critical environments This is not a pure ML position. It is a model-based tracking and estimation role with operational deployment responsibility.

we are seeking a skilled failure analysis (fa) engineer with expertise in x-ray inspection techniques to join our av platform team. the ideal candidate will specialize in using advanced x-ray imaging and other analysis methods to investigate product failures, identify root causes, and provide actionable insights to improve product quality and reliability what will your job look like?
perform detailed failure analysis using x-ray imaging systems and related diagnostic tools to inspect electronic components, assemblies, and materials.
interpret and analyze x-ray images to detect structural anomalies, defects, voids, cracks, delamination, and other failure mechanisms.
develop and optimize x-ray inspection procedures and protocols for failure analysis and quality control.
prepare TEST specimens: cutting, mounting, grinding, polishing and chemical etching
collaborate with product engineering, Quality Assurance, and manufacturing teams to support product development, troubleshooting, and continuous improvement efforts.
prepare detailed technical reports documenting findings, root cause analyses, and recommended corrective actions.
support reliability testing and failure mode analysis for new and existing products.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as a SOC physical design engineer, you will collaborate with functional design, design for testing (dft), architecture, and packaging engineers. additionally, you will solve technical problems with micro-architecture and logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.the ai and infrastructure team is redefining whats possible. we empower customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include , cloud customers, and billions of our  users worldwide. we're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for cloud, global networking, data center operations, systems research, and much more.
responsibilities
define and drive the implementation of physical design methodologies.
take ownership of one or more physical design partitions or top level.
drive to the closure of timing and power consumption of the design.
contribute to design methodology, libraries, and code review.
define the physical design related rule sets for the functional design engineers.

our company is a cutting-edge national facility supporting our computing research and development for both academia and industry. the iqcc is managed and operated by our machines (qm), the global leader in quantum computing control systems. our state-of-the-art lab includes advanced infrastructure with several dilution refrigerators and a wide array of quantum and classical devices.
the iqcc offers unique opportunities for talented phd students seeking an internship opportunity at a world-class facility. we are looking for brilliant, versatile, and fast-learning interns with a strong can-do attitude to become a part of the core iqcc team, working on a our computer with 20+ superconducting qubits, assisting in its calibration, integration and assembly, through qms opx1000 control platform. he/she will gain unique experience with the worlds top cryogenic systems and participate in cutting edge research projects with the leaders of industry and academia. the ideal candidate should have experience working with our systems and should be ready to move to israel to work on-site in the iqcc for a period of 4-6 months.
responsibilities:
support the calibration and optimization of superconducting qubits chip
participate in research projects that aim to develop new calibration protocols for faster and higher quality gates
gain a deep understanding of our state-of-the-art control system
assist in the day-to-day operation of the lab.

in this role, you will help build socs by driving quality and reliability processes from the integrated circuit (ic) perspective. working with various cross-functional teams, you will develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute TEST plans. within the larger organization, you will collaborate with global hardware quality and reliability, silicon design, validation, and engineering teams. you will have an understanding of ic flows, wafer processing, testing, qualification, yield, reliability, and failure analysis.the ml, systems, & cloud ai (msca) organization at google designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define and lead qualification hardware and TEST developments in front of internal teams and external vendors.
define and execute silicon and package qualification activities (e.g., htol, elfr, esd/lu, b/hast, thb, etc.).
extract, manipulate, and analyze large volumes of data from silicon and package qualification programs (e.g., htol, elfr, esd, lu, uhast, tct, etc.), high volume mfg, and field returns to identify failure mechanisms, reliability trends, and opportunities for yield, quality, and reliability improvement.
own cross-functional investigation of ic quality and reliability issues to identify root causes and develop solutions (e.g., rma triage, analytics, failure analysis, etc.).
develop and implement physics-based statistical quality and reliability models (e.g., elf, tddb, nbti, hci, time zero failures, etc.) to predict silicon device failure mechanisms, degradation patterns, and lifetime behaviors.

The Camera System Engineering team in Israel is looking for a system engineer directly responsible for the design of calibration, simulation and test for new camera systems. This engineer works closely with Hardware design, Algorithms, Data analysis and Operation groups to ensure the success of future our products.

Design, specification, development and deployment of camera calibration, simulation and tests.
Responsibilities include:
Develop, optimize and debug the algorithms responsible for test, calibration and image processing
Cooperate with cross functional teams to specify and implement the end-to-end test coverage
Analyze large scale factory data, and formulate critical reports of the product performance
Analyze and debug failures, and come up with Hardware and Software solutions