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לפני 13 שעות
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Staff Embedded Firmware Engineer, High Speed DSP
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Staff Embedded Firmware Engineer for High-Speed DSP, you will architect and define the low-level firmware and control loops powering the world's most advanced physical-layer communications silicon. Sitting at the critical intersection of digital signal processing (DSP), hardware-software co-design, and real-time systems, you will lead the development of adaptive algorithms, error correction (FEC), and link-telemetry frameworks. Your work will directly bridge the gap between high-performance hardware pipelines and our planetary-scale AI infrastructure, transforming complex communication systems theory into reliable, real-time silicon execution.
Responsibilities
Define the long-term firmware roadmap and hardware-software partitioning for physical-layer interfaces, determining the optimal balance between hardware-fixed logic and programmable firmwarm.
Architect advanced "in-situ" monitoring systems and firmware-driven diagnostics to track physical-layer link health, Bit Error Rate (BER) trends, and channel quality across millions of ports in real-time.
Design, model, and implement bare-metal or RTOS firmware to control high-speed transceivers, managing real-time adaptive loops, clock and data recovery (CDR), and physical-layer calibration.
Partner with TPU Systems, Networking Software, and High-Performance Computing (HPC) teams to ensure silicon firmware integrates seamlessly with global cluster management and collective communication frameworks.
Identify and de-risk hardware-software interface bottlenecks (e.g., register maps, driver latencies, and boot-up sequencing) that impact our AI infrastructure.
Requirements:
Minimum qualifications:
Bachelors degree in Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
10 years of industry experience in embedded systems/firmware, communication systems engineering, or digital signal processing (DSP) development.
Experience developing embedded software (C/C++) for high-speed physical-layer interfaces (PHY), digital transceivers, or communication subsystems.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
Expertise in Forward Error Correction (FEC) algorithms and advanced modulation schemes.
Track record defining firmware framework specifications, register maps, and Silicon Lifecycle Management telemetry for high-volume networking or AI silicon.
Background in wireless communications with deep domain knowledge of channel modeling, noise mitigation, and digital transceiver architectures.
This position is open to all candidates.
 
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לפני 15 שעות
Location: Tel Aviv-Yafo
Job Type: Full Time
we are looking for a Research Scientist - Sovereign AI Research.
We are hiring across the following specializations. We expect depth in at least one area and the intellectual range to collaborate across them.
Computer Vision: object detection, segmentation, multimodal grounding, vision-language models, contrastive and self-supervised representation learning, low-resource and few-shot visual recognition.
NLP / Speech: LLMs, NERs, relation extraction, span-based and generative IE, semantic textual similarity, multilingual and cross-lingual transfer.
Reinforcement Learning: MDPs, POMDPs, model-based and model-free RL, Online Offline methods, reward modeling, sim-to-real transfer, compute-aware planning.
Graph Learning: GNNs, graph clustering, community structure, generative methods, knowledge graph embeddings, dense and sparse semantic retrieval.
Optimization: convex and nonconvex optimization, constrained and Lagrangian methods, combinatorial and integer programming, knowledge distillation (response, feature, and relation-based), test-time optimization, Bayesian optimization, resource-aware inference.
Representation Learning: contrastive learning, self-supervised and unsupervised pre-training, disentangled representations, metric learning and embedding spaces, cross-modal and multimodal alignment, meta learning (hypernetworks), transfer learning and domain adaptation, probing and interpretability of learned representations, world models.
Neurosymbolic AI: neuro-symbolic integration, differentiable theorem proving, inductive logic programming (ILP), probabilistic soft logic (PSL), causal inference and structural causal models (SCMs), programmatic and compositional reasoning
Responsibilities:
Define and execute a research within your track, experiments, quality gates, and upper bounds in rigorous manner.
Collaborate across tracks on system integration and cross-disciplinary research.
Collaborate work with engineering teams until production.
Mentor junior researchers and contribute to a culture of technical excellence
Requirements:
PhD in Computer Science, Electrical Engineering, Mathematics, or a related field OR a Distinguished MSc with a strong publication record or demonstrated research impact equivalent to doctoral-level work (5+ years of experience).
Strong publication record at top venues (NeurIPS, ICML, ICLR, ACL, CVPR, ICCV, EMNLP, AAAI, or equivalent)
Proficiency in Python and deep learning frameworks (PyTorch, JAX)
Demonstrated ability to drive independent research projects end-to-end
Hands-on experience with data pipelines: sourcing, structuring, cleaning, and transforming raw data into training-ready assets is treated here as a core research competency, not a support task
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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1 ימים
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time and Hybrid work
we are looking for a AI Applied Scientist - Insights & Recommendations.
As AI Applied Scientist, youll be at the intersection of advanced technology and meaningful impact with clear business cases. You will have access to real-time (RT) big data from multiple Sensors & Data sources, and a chance to discover, explore research, and develop cutting-edge models that directly impact industrial manufacturers around the globe. As part of the Applied AI/ML Science team , you will have the opportunity to continuously grow and learn while building and deploying advanced models directly into our products, and stay at the forefront of the world's technologies, witnessing firsthand their impact on our customers.
A Day In Your Life:
Own the algorithm lifecycle from problem definition and data analysis to prototyping and delivering production-ready models.
Combine classic methods with inference techniques: statistics, Time series, Deep learning, anomaly detection, Recommendation Systems, Transformers, and Inference to extract data-driven insights.
Research, design, and build Agentic applications on top of sensor time-series data, textual data, images, ML applications, and other various data sources.
Engage with customers and collaborate with our product team to develop innovative solutions utilizing new types of data.
Leverage modern technologies: work with cloud-based big data platforms for storage, distributed processing, LLMs and agents (GPT, Claude, Gemini), defining & building Gurdrails, reasoning chain as function call, planning, ML-based vectorization and embeddings, and stream analysis.
Requirements:
M.Sc., or Ph.D. in Electrical Engineering, Computer Science, Physics, Mathematics, or a related field.
5+ years of experience in ML applications in modeling Time-series data, & ML-based vectoring, and Embeddings for insight & recommendations systems (Transformers included) - Mandatory
2+ years of experience in LLM and Agentic applications, Eval tools, methods, and workflows (HITL, LLM-as-a-judge, deterministic, Metrics & Embeddings), Fine-Tuning, and AI workflows and lifecycle (e.g. LangSmith, CrewAI, LangGraph, Embedding (BERT, w2v, FastText, FastEmbed, GloVe, etc.), Tokenizations (GPT. TikToken, Token validators, etc.), & Vector Similarities & search methods
Proficiency in Python for model development, deployment, and monitoring.
Experience working on Agile teams with a passion for fast iterations, feedback, and continuous learning.
Proven ability to collaborate with diverse, cross-functional groups, including product managers, infrastructure, and data engineering teams.
The ability to translate research into scalable, production-ready solutions.
Experience in anomaly detection and AI/ML - an advantage.
Experience in feature engineering-based signal processing - an advantage
Experience in optimizing costs of API calls - Nice to have
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Silicon Test and DFT Engineer, Cloud
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.The AI and Infrastructure team is redefining whats possible. We empower customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
We're behind groundbreaking innovations, empowering the development of AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Collaborate with Architecture, Design and Verification teams to develop new product bring-up, validation, characterization, and qualification strategies and manufacturing test solutions for new High Performance Computing (HPC) products in advanced process technologies.
Verify test solutions on pre-silicon models (simulation or emulation) and develop Automated Test Equipment (ATE) test modules and binning flows.
Develop and validate test programs on Automated Test Equipment (ATE) platforms for new product integration (NPI) in preparation for high-volume manufacturing (HVM), working with ATE vendors and internal cross-functional teams.
Manage product sustainment support, including analyzing volume data, improving test time and yield, assessing test escapees and return merchandise authorizations (RMAs), localizing failures, implementing containment measures, and partnering with design, manufacturing, and quality and reliability teams to identify root causes and implement corrective actions.
Build tools, flows and methodologies to continuously improve and automate the testing life-cycle.
Requirements:
Minimum qualifications:
Bachelor's degree in Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience in test engineering.
Experience in pre-silicon validation, test content generation, automatic test equipment (ATE) program development, and post-silicon enabling from new product introduction (NPI) through high-volume manufacturing.
Experience with ASIC test methodologies (MBIST, ATPG, DFT, SerDes, and sensors).
Experience with Python, Java, C# or C/C++ and Advantest or Teradyne ATE platforms.
Preferred qualifications:
Masters in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
10 years of experience in test engineering, including product engineering.
Experience with CPU/GPU SoC architecture, design, validation and debug.
Experience in advanced testing methodologies and data analysis, including system to tester correlation, yield and test time analysis and improvement, etc.
Demonstrated expertise in developing automations for pre-silicon verification and post-silicon test-generation/test-program domains.
Inquisitive and motivated to venture into, and improve, all aspects of post-silicon testing from definition to realization.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Junior SoC IP Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our Platforms Infrastructure Engineering team designs and builds the
hardware and software technologies that power all of our services. Our computational challenges are complex and unique, enabled by custom hardware designed and made in-house. As a hardware engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will see those systems from concepts all the way through to high-volume manufacturing. Your work has the potential to shape the machinery that goes into our data centers, affecting millions of users.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform RTL development (coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure and ASIC silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
1 year of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
Experience with design sign off and quality tools (Lint, CDC , etc.).
Preferred qualifications:
Master's degree or PhD in Computer Science, or a related technical field.
Knowledge in one of these areas: Peripheral Component Interconnect Express (PCIe), Universal Chiplet Interconnect Express (UCIe), Double Data Rate (DDR), Advanced eXtensible Interface (AXI), Advanced RISC Machine (ARM) processors family.
Knowledge of high performance and low power design techniques.
Knowledge of assertion-based formal verification.
Knowledge of SOC architecture.
Excellent problem-solving and debugging skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8783541
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SOC and IP Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
We're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital reasoning design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
Experience with reasoning synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power and design techniques.
Experience in reasoning design and debug with Design Verification (DV).
Preferred qualifications:
Experience with a scripting language like Python or Perl.
Experience with design sign-off and quality tools (e.g., Lint, clock domain crossing (CDC), etc.).
Knowledge of System on a chip (SOC) architecture and assertion-based formal verification.
Knowledge of design techniques.
Knowledge in one of these areas: Peripheral Component Interconnect Express (PCIe), Universal Chiplet Interconnect Express (UCIe), Double Data Rate SDRAM (DDR), Advanced Extensible Interface (AXI), ARM processors.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8783535
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SoC and IP Design Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
We're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.).
Perform Register-Transfer Level (RTL) coding (coding and debug in Verilog, SystemVerilog), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power closure activities.
Contribute to test plan and coverage analysis of the block and SoC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques.
Experience with design sign-off and quality tools (e.g., Lint , CDC , etc.).
Experience with SoC or IP architecture.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Knowledge of high-performance and low-power design techniques, assertion-based formal verification, Field-programmable Gate Array (FPGA) and emulation platforms, and SoC architecture.
Knowledge in one of the following areas such as Double Data Rate (DDR)/Low Power Double Data Rate (LPDDR), High-bandwidth memory (HBM).
Excellent problem-solving and debugging skills.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SoC Test Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Collaborate with Architecture, Design and Verification teams to develop new product bring-up, validation, characterization, and qualification strategies and manufacturing test solutions for new High Performance Computing (HPC) products in advanced process technologies.
Verify test solutions on pre-silicon models (simulation or emulation) and develop ATE test modules and binning flows.
Develop and validate test programs on Automated Test Equipment (ATE) platforms for new product integration (NPI) in preparation for high volume manufacturing (HVM), working with ATE vendors and internal cross-functional teams.
Product sustain support, including volume data analysis, test time and yield improvements, assess test escapees and RMAs, localize failures, implement containment measures and partner with design, manufacturing, quality and reliability teams to root cause and implement corrective actions.
Develop tools, flows and methodologies to continuously improve and automate the testing life cycle.
Requirements:
Minimum qualifications:
Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or related
8 years of experience in test engineering
Experience in pre-silicon validation, test content generation, ATE program development, and post-silicon enabling from new product introduction through high volume manufacturing.
Experience with ASIC test methodologies (e.g., mbist, atpg, dft serdes, sensors).
Experience in Python, Java, C# or C/C++ and Advantest or Teradyne ATE platforms.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
10 years of experience in test engineering, including product engineering.
Experience with CPU/GPU SoC architecture, design, validation and debug.
Experienced in advanced testing methodologies and data analysis, including system to tester correlation, yield and test time analysis and improvement, etc.
Demonstrated expertise in developing automations for pre-silicon verification and post-silicon test-generation/test-program domains.
Ability to be motivated to venture into, and improve, all aspects of post-silicon testing from definition to realization.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required DDR Validation Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Define, develop, and execute post-silicon validation test plans on both pre-silicon emulation setups and physical silicon platforms in the lab.
Lead the bring-up of silicon, troubleshooting and identifying root causes of complex hardware and software issues.
Work closely with Architects, Design Engineers, Firmware/Software developers, and production teams to drive bug fixes and ensure feature functionality.
Provide comprehensive functional coverage for our custom designs, driving the transition from a prototype chip to a fully realized product deployed globally.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience in embedded code development (e.g., C/C++ or Python).
Experience in Double Data Rate (DDR) PHY or Memory Controller (MC) post-silicon validation activities.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with functional tests for silicon validation, bring-up, characterizing, and qualifying silicon.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8783361
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Emulation Hardware Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our platforms, we make our product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Maintain and upgrade emulation models and infrastructure and act as a primary interface to emulation vendors.
Explore emulation methodologies, gather feedback from the team and customers, and implement emulation workflows and methodologies.
Create tooling and automation to support emulation Electronic design automation (EDA) tools, licensing, and job management in our infrastructure.
Support emulation team members with debugging hardware, tooling, and project-specific issues.
Help to bring up external interfaces (e.g., DDR, Peripheral Component Interconnect Express (PCIe), Ethernet, etc.) on the emulation platforms and create standalone test cases for tool issues encountered in the emulation compile and runtime flows.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
4 years of experience with emulation systems (e.g., ZeBu Server, Palladium, Veloce), compilation, debug, performance and methodology enhancements.
Experience with coding and scripting in C, C++, Perl, TCL, or Python.
Experience with associated EDA tools, automation, and flow enhancements.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
Experience with hardware verification concepts and tools (e.g., simulation, coverage, assertions, CPU Arch, SoC, fabric, networking).
Experience with FPGA systems (e.g., EP, HAPS, Protium).
Experience with hybrid emulation or speed bridges.
Experience with coding in Verilog/SystemVerilog for design.
Experience with design debug tools (e.g., Verdi, Verisium).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8783302
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior Silicon DFT Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will play a crucial role in Design for Testing (DFT) Architecture and DFT design, and support devices of extreme complexity to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality matrix throughout the project life-cycle, and providing sign-off DFT to tapeout.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs.
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team.
Lead DFT execution of a silicon project (e.g., planning, execution, tracking, quality, and signoff).
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
8 years of experience in Automatic Test Pattern Generation (ATPG) methods.
Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
Experience in leading DFT activities throughout an ASIC development flow.
Preferred qualifications:
Master's degree in Electrical Engineering or a related field.
Experience in JTAG and iJTAG protocols and architectures.
Experience in post-silicon test or product engineering.
Experience in SoC cycles, silicon bring-up, and silicon debug activities.
Knowledge of fault modeling techniques.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8783248
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1 ימים
Location: Herzliya
Job Type: Full Time and Hybrid work
Were looking for a Team Leader who is a tech-enthusiast with a drive for excellence, and an out-of-the-box mindset to satisfy business needs in a complex payment solution environment.
What youll do:
Collaborate closely with Product, Design/UX, DevOps, and other R&D teams
Lead an autonomous team of software engineers who are working closely with product management for achieving business goals
Put special focus on developing the team
Provide technical authority to your team by demonstrating a hands-on leadership style
Be responsible for the overall design, development, architecture, code quality, and production environment deployment of your team
Requirements:
S. in computer science or equivalent
5 + years of experience as a server side developer, all the way from DB to UI (using C# - a must!, REST APIs, and asynchronous communication with Queues/Streams)
3+ years of experience with advance SQL (MSSQL/Oracle/MySql/PostgreSQL etc.)
2+ years of managerial experience - a must!
Broad knowledge of OOP and design patterns
Team player attitude and mentality
Experienced and passionate about managing and growing people
Experience in engineering best practices (code-reviews, testing coverage, agile methodologies)
Ambitious and eager to learn new things
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8782947
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1 ימים
Location: Haifa
Job Type: Full Time
We are looking for
For our company site in Haifa, we are looking for a Technical Manager to lead a fighter aircraft upgrade program for a foreign air force
.Join a meaningful and complex project involving the leadership of advanced engineering activities in the aerospace and defense industry. This role includes collaboration with multidisciplinary teams בארץ ובעולם, leading development and integration processes, and contributing directly to advanced operational capabilities
In this role you will
Lead all engineering activities from the design phase through aircraft delivery to the customer
Work with subcontractors to define work scope and implement purchased systems
Collaborate with internal development teams to establish development and integration infrastructures
Coordinate cross-functional engineering teams including environmental engineering, E3, mechanics, and additional disciplines
Be responsible for all development stages including requirements definition, implementation, integration and testing, safety, flight testing, and customer support.
Requirements:
B.Sc. in Electrical Engineering, Computer Engineering, or Aeronautical Engineering
At least 3 years of experience in system engineering or systems integration
Experience in technical management of complex systems - Advantage
Familiarity with avionics systems
Teamwork abilities, interface management skills, and system-level thinking.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8782936
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1 ימים
Location: Herzliya
Job Type: Full Time
The WSSI (Windows Silicon System Integration) team is looking for an experienced Silicon Design Verification Team Lead to lead verification for complex silicon subsystems that are part of advanced solutions delivered in Windows client products.

This is an opportunity for an excellent DV leader to combine people leadership with meaningful hands-on technical contribution. You will lead a silicon engineering team that includes design verification, silicon design, and physical design engineers, while serving as the technical anchor for the team's verification strategy, execution, and quality.

The team works on complex security-oriented silicon subsystems that require rigorous pre-silicon verification and close collaboration with architecture, design, firmware, system engineering, and physical design partners to deliver robust silicon quality.

We are looking for a leader who is passionate about building excellent teams, driving rigorous execution, contributing hands-on to complex verification challenges, and continuously improving verification methodologies - including applying modern AI-assisted techniques to improve productivity, debug efficiency, and verification quality.

Responsibilities
Lead, grow, and mentor a silicon engineering team that includes design verification, silicon design, and physical design engineers, while fostering a culture of technical excellence, ownership, collaboration, and continuous learning.
Own and drive the verification strategy for complex silicon subsystems from planning through execution, closure, and emulation readiness.
Provide substantial hands-on technical contribution and leadership in verification planning, testbench architecture, debug, coverage analysis, regression quality, and verification closure.
Build and promote modern verification workflows, including AI-assisted techniques that improve verification environment development, automation, debug efficiency, coverage analysis, and execution quality.
Define verification plans, quality metrics, regression strategy, coverage goals, and emulation readiness plans aligned with project milestones.
Collaborate closely with architecture, design, system engineering, firmware, and physical design partners to identify risks early, resolve complex issues, and deliver high-quality silicon subsystems.
Requirements:
Qualifications
B.Sc., M.Sc., or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field.
Proven experience and technical excellence in pre-silicon design verification for complex IPs, subsystems, or SoCs, including subsystem integration, and third-party IP integration.
Significant hands-on experience with modern DV methodologies, verification planning, testbench development, regressions, coverage analysis, debug, and verification closure.
Experience as a people manager or technical leader driving verification work across multiple engineers.

Preferred Qualifications
Proficiency in SystemVerilog-based verification environments and methodologies such as UVM, assertions, constrained-random verification, and coverage-driven verification, along with Python-based automation and modern verification infrastructure workflows.
Experience applying AI-assisted techniques to improve silicon design or verification productivity, debug, coverage, automation, or workflow efficiency.
Hands-on experience with Python, Linux, Git-based development workflows, and automation infrastructure.
Experience with formal verification, low-power verification, performance verification, or subsystem-level verification.
Experience with security-oriented silicon subsystems, including crypto engines, memory protection, secure boot, trusted execution, or related hardware security domains.
Experience with emulation platforms such as Palladium.
Experience leading or working in teams that include both design and verification engineers.
This position is open to all candidates.
 
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8782806
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1 ימים
Location: Herzliya
Job Type: Full Time
The WSSI (Windows Silicon System Integration) team is looking for a Senior Silicon Designer to help design complex silicon subsystems that are part of advanced solutions delivered in Windows client products.
This is an opportunity for an excellent silicon engineer to take meaningful technical ownership in a dynamic, agile, and highly collaborative environment. You will work on advanced subsystem design spanning microarchitecture, RTL implementation, integration, and design quality, with close collaboration across architecture, verification, firmware, system engineering, and physical design teams.
The role focuses on complex security-oriented silicon subsystems. We are looking for someone who combines strong design fundamentals with curiosity, ownership, and the motivation to learn and apply modern techniques - including AI-assisted workflows - to improve silicon development productivity and quality.

Responsibilities
Own and drive microarchitecture and RTL design for complex silicon blocks and subsystems, translating architecture and system requirements into clean, efficient, and high-quality hardware implementations.
Collaborate closely with verification, firmware, system engineering, architecture, and physical design partners to define interfaces, debug complex issues, manage technical risks, and deliver robust silicon solutions.
Contribute to subsystem integration, design reviews, quality checks, synthesis readiness, timing considerations, and design handoff flows.
Explore and apply modern silicon development workflows, including AI-assisted techniques for design productivity, debug, documentation, and quality improvements.
Act as a technical leader within the team by mentoring others, raising the engineering bar, and helping drive execution in a fast-moving environment.
Requirements:
B.Sc. or higher in Electrical Engineering, Computer Engineering, or a related technical field.
Proven experience and technical excellence in RTL design for complex IPs, subsystems, or SoCs.
Proven hands-on experience with Verilog/SystemVerilog, microarchitecture definition, RTL implementation, design reviews, and design quality practices.

Preferred Qualifications:
Experience applying AI-assisted techniques to improve silicon design productivity, debug, documentation, automation, or workflow efficiency.
Experience with security-oriented silicon subsystems, including crypto engines, memory protection, secure boot, trusted execution, or related hardware security domains.
Experience working across key parts of the silicon development lifecycle, including verification collaboration, integration, synthesis readiness, timing considerations, and design closure.
Experience with low-power design, performance optimization, clock/reset architecture, CDC/RDC, lint, synthesis, or timing closure.
Experience acting as a technical leader, design owner, or mentor for other engineers.
Strong problem-solving skills, ownership mindset, and ability to drive technical work independently while collaborating effectively across disciplines.
High motivation, curiosity, and willingness to learn new domains, tools, and methodologies.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8782798
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