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Our Physical Design group operates in a dynamic, startup-like environment that values deep technical expertise and high-level execution. Each engineer holds end-to-end responsibility - from initial definition and constraints development to execution and full signoff. You will work closely with Design and Architecture teams on RTL modifications and design reviews to ensure seamless convergence.
Were looking for an Experienced Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner, leading the process from RTL to GDS .
Lead floorplan exploration in collaboration with Front-End and Architecture teams.
STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis.
Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks.
Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area).
Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

Which department will you join?
Our Physical Design group operates in a dynamic, startup-like environment that values deep technical expertise and high-level execution. Each engineer holds end-to-end responsibility - from initial definition and constraints development to execution and full signoff. You will work closely with Design and Architecture teams on RTL modifications and design reviews to ensure seamless convergence.
Were looking for a Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner, leading the process from RTL to GDS .
Lead floorplan exploration in collaboration with Front-End and Architecture teams.
STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis.
Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks.
Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area).

Our Physical Design group operates in a dynamic, startup-like environment that values deep technical expertise and high-level execution. Each engineer holds end-to-end responsibility - from initial definition and constraints development to execution and full signoff. You will work closely with Design and Architecture teams on RTL modifications and design reviews to ensure seamless convergence.
Were looking for an Experienced Physical Design Engineer to join our growing team, and take a key role in developing our next-generation SoC from definition to Tape-Out.
What will your job look like:
Hands-on physical design block owner from RTL to GDS with horizontal ownership.
Floorplan exploration and collaboration with front-end and architecture teams.
Synthesis exploration and final synthesis including: SDC definition, Scan insertion, Lint, LEC, UPF-LP & Spyglass verification.
Place & Route: from Synthesis to final layout and signoff verification on all tools and floors, with target to achieve best PPA.
STA: timing analysis, working with Sub System and Full Chip owners to manage block and top level constraints for synthesis, P&R and signoff.
Signoff : on all physical design domains- STA, IR/EM, Physical Verification, Logic Equivalent Checking, Low Power Verification.

our company's EyeQ Platform Group (EPG) is seeking a motivated Formal Verification Engineer to join our team and contribute to development of hardware verification environments.
This position offers an opportunity to apply formal methods to verify the correctness of various complex digital systems.
This is an exciting opportunity to join a team of talented engineers, working cutting edge technologies in the field of autonomous vehicle.
What will your job look like:
Be the owner of formal verification environment from first draft to sign-off stage
Apply formal methods to verify the correctness of various complex digital systems
Work with HW architects\designers to define assumptions, rules and cover properties
Help define the formal verification methodology and environment to be applied by the team
Explore new Formal methods and Tools
Work with tools like Cadence JasperGold, Verisium manager, Xcelium, Indago
Analyze verification results, identify bugs, and collaborate with engineers to resolve design issues
Develop generic formal blocks\functions of commonly used logic, to be later used off the shelf.

abra is seeking for an Senior FPGA Engineer This role require close collaboration with multidisciplinary teams, including hardware, software, verification, and system engineers, to deliver high-performance, mission-critical FPGA solutions—from concept and design through development and production, all the way to integration and operational deployment. Full-time position, Sunday–Thursday, in Holon.

Required Chip Test Engineer
About The Position
The Chip Test Engineer plays a crucial role in designing, developing, and implementing automated test for IC chips and systems for Automotive industry. The Test Engineer is responsible to define and develop tests, design test features, program test scripts, and analyze test results to ensure the quality and functionality of products. The Test Engineer collaborates with cross-functional teams to troubleshoot issues, improve test processes, and support product development efforts.
Responsibilities
Develop and implement test strategies, plans, and procedures for ATE systems to ensure comprehensive testing of ICs.
Design and develop test features, test programs, and test scripts for automated test environment (ATE) based on product specifications and requirements.
Collaborate with design engineers, product manager, production vendors and manufacturing teams to understand product functionality, performance requirements, and testability considerations.
Conduct feasibility studies and risk assessments to identify potential challenges and develop mitigation strategies for test development and implementation.
Develop test program based on code languages C++ ,Java and Python.
Debug, troubleshoot, and resolve issues with ATE hardware, software, and test scripts to ensure reliable and accurate test results.
Analyze test data and results to identify trends, anomalies, and potential defects, and provide feedback to design and development teams for product improvement.
Develop and maintain documentation for test procedures, specifications, and configurations.
Collaborate with vendors and suppliers to evaluate and select ATE equipment, components, and software tools that meet project requirements and performance standards.
Stay abreast of industry trends, advancements in test technologies, and best practices in automated testing to drive continuous improvement in test processes and methodologies.

Were looking for a talented Radar System Integration Engineer to join our innovative System Engineering group.
Responsibilities
Integrate multidisciplinary full radar system including HW Platform, ASIC, RFIC, SW, ALGO
Troubleshoot and debug our Radar, ASIC and FPGA platforms
Define, implement and execute acceptance tests plans, procedures, and reports
Define new features and HW requirements for full system optimization
Simulate and analyze mix signals system data
Validate system performance.

We're looking for an exceptional senior Chip Design Engineer to join our Nitro team and help shape what comes next. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match- powering hundreds of thousands of businesses across 190 countries.

As a Senior Chip Design Engineer on the Nitro team, you will take full end-to-end ownership of one or more critical IP blocks within the product, guiding them from micro-architecture definition through RTL design, debug, synthesis, timing closure, and final sign-off before tape-out. Your work will ship in silicon that powers AWS at global scale.
You'll partner closely with the Verification and Emulation teams to shape test plans, review coverage, and close gaps early in the design cycle. Beyond your own IP, you'll collaborate across disciplines with Product Definition, Software, Physical Design, and Verification teams to deliver a fully integrated, production-ready chip.

Key job responsibilities
Full ownership of one or more IPs within the product:
Micro-architecture definition.
RTL coding and debug.
Synthesis and timing closure.
Sign-off before tape-out.
Supporting the Verification and Emulation teams: Test plan development, coverage review.
Ensuring the chip meets quality and reliability standards.
Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical Design.

As a System Integration Engineer on our DDR team, you'll own end-to-end interface development and integration across the full product lifecycle - from early concept through silicon bring-up to production debugging at scale. You'll be part of developing the advanced memory technologies that power our AGI fleet.

Day-to-day, you will:
1. Shape interface design strategies - influence architectural decisions that define next-generation memory subsystems.
2. Drive system integration - bring together hardware, firmware, and software to deliver optimal design implementations.
3. Debug at cloud scale - leverage data from the world's largest public cloud to solve complex cross-domain challenges.
4. Collaborate with industry leaders - work directly with the top DRAM manufacturers in the world.
5. Raise the bar - set quality standards and drive continuous improvements in performance, reliability, and cost.

The Senior Hardware Test Engineer is responsible for developing, implementing, and sustaining test processes and equipment used in the manufacturing of hardware products. This role ensures that products meet quality, reliability, and performance standards through robust test strategies, automation, and continuous improvement. The engineer acts as a bridge between design engineering, manufacturing operations, and quality assurance, supporting new product introductions (NPI) through to mass production and sustaining phases.
This is a great opportunity to be part of one of the fastest-growing AI infrastructure companies in history, an organization that is in the center of the hurricane being created by the revolution in artificial intelligence.
we are the data platform company for the AI era. We are building the enterprise software infrastructure to capture, catalog, refine, enrich, and protect massive datasets and make them available for real-time data analysis and AI training and inference. Designed from the ground up to make AI simple to deploy and manage, our company takes the cost and complexity out of deploying enterprise and AI infrastructure across data center, edge, and cloud.
Our success has been built through intense innovation, a customer-first mentality and a team of fearless workers who leverage their skills & experiences to make real market impact. This is an opportunity to be a key contributor at a pivotal time in our companys growth and at a pivotal point in computing history.
Role and Responsibilities:
Test Development & Validation
Design, develop, and implement test plans, test fixtures and infrastructure.
Collaborate with R&D to define test requirements early in the product lifecycle.
Develop test scripts and automation software (Python, LabVIEW, C#, etc.) to improve coverage and efficiency.
Validate test coverage, yield, and reliability through statistical analysis (GR&R, Cpk, SPC).
New Product Introduction (NPI)
Support EVT, DVT, and PVT phases with test readiness and execution.
Lead test process transfer to contract manufacturers (CMs) or ODM partners.
Train CM engineers/technicians on test systems and procedures.
Ensure compliance with safety, regulatory, and customer requirements.
Manufacturing Support & Continuous Improvement
Monitor production test yields, debug failures, and drive root cause analysis (RCA).
Implement corrective actions and continuous improvements to reduce test time, cost, and false failures.
Maintain and calibrate test equipment and fixtures.
Support ECO (Engineering Change Orders) by updating test plans and equipment accordingly.
Cross-Functional Collaboration
Work closely with hardware, firmware, and reliability engineers to improve product testability and robustness.
Partner with Quality and Operations to ensure smooth scaling into mass production.
Engage with suppliers and CM partners on test strategy alignment.

We are looking for an Infrastructure Team Leader to lead and manage a highly skilled team of 4-5 engineers, responsible for Emulation, CAD, DevOps, compute infrastructure, and automation.
This role combines 50% hands‑on and 50% manageiral technical leadership and end‑to‑end ownership of infrastructure, tooling, and release flows.
The position has a significant impact on productivity, quality, and time‑to‑market of the companys silicon products and is reporting directly to the director of the department.
Responsibilities
Lead and mentor the Infrastructure team, including CAD, DevOps, automation, and emulation activities.
Own the definition, development, and maintenance of infrastructure: Emulation, design flows, verification flows, releases, automation, TFS Azure DevOps and CI/CD pipelines.
Drive continuous improvement of infrastructure reliability, performance, scalability, and usability.
Take end‑to‑end responsibility, cross BU, cross site VLSI releases, environments, and production readiness.
Collaborate closely with different stakeholders in the HW and SW RnD teams to align infrastructure with project needs.

We are seeking an experienced and commercially driven Director of Licensing to lead the licensing strategy and execution for our semiconductor intellectual property (IP) portfolio. This role is responsible for efficiently driving complex product and commercial contract negotiations with semiconductor manufacturers, fabless companies, and system integrators.
The ideal candidate combines proven experience in IP licensing (commercial and legal), technology commercialization, complex negotiation and business acumen, strategic deal making skills, with knowledge of the semiconductor industry being a plus.
Key Responsibilities
Portfolio Monetization & Licensing Strategy
Work closely with leadership in Product Divisions, Sales , Finance and Legal to develop strategies to maximize revenue from the companys IP portfolio.
Evaluate opportunities for licensing expansion, renewals, and new use cases.
Support IP valuation, competitive analysis, and market positioning.
Define optimal licensing models and pricing models that support and drive sustainable and profitable growth
Deal Structuring & Negotiation & Enforcement
Work closely with leadership in Product Divisions, Sales, Finance and Legal to develop and maintain commercial proposal templates and license agreement templates that increase and streamline deal process efficiencies and align with business objectives.
Support the Sales team globally throughout complex commercial and legal negotiations, from proposal to deal closing stages and manage contract lifecycle thereafter.
Coordinate with Sales, Finance and Legal teams on reporting, compliance, and enforcement of contract terms.

As a CAD Engineering Student, you will join an experienced CAD, DevOps, and Emulation team, working on cutting-edge VLSI infrastructure. You will support automation, release processes, and emulation flows while gaining hands-on exposure to full chip development environments.
Responsibilities:
Support VLSI infrastructure, automation flows, and release processes.
Assist in developing and maintaining CAD/DevOps scripts and tools
Participate in emulation activities and environment setup
Collaborate with design and verification teams to improve engineering efficiency.

We are looking for you to join our emulation team focusing on the creation, deployment, and support of advanced emulation environments. In this highly visible role, you will be at the center of a chip design effort collaborating with all disciplines, with a critical impact on getting functional products to millions of customers quickly.

As a senior emulation engineer, you will have the responsibilities as follows: Work closely with emulation, architecture and verification teams to create and enhance emulation environments. Work with the leading emulation vendors to debug issues and deploy new capabilities. Develop new emulation workloads and platforms to enhance user productivity . Develop high performance emulation models and transactors in system Verilog and C/C++ . Support multiple emulation environments using the latest emulation techniques Root cause failing SoC/Processor tests and emulator environment issues.