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Requirements:
What we need to see:
MSc Graduate in Computer Science, and currently pursuing PhD.
Experience in algorithm development.
Excellent programming, debugging and code design in C++.
Clever with sharp learning curve.
Strong interpersonal skills, both written and verbal.
Ability to work independently with minimal direction.

Ways to stand out for the crowd:
An advanced degree in formal verification or static analysis.
Experience in formal verification development.

Requirements:
What we need to see:
A Bachelors Degree in Electrical Engineering or Computer Science.
Exposure to design and verification tools.
15+ years of hands-on pre-silicon verification experience.
Strong interpersonal skills and ability & desire to innovate.

Ways to stand out from the crowd:
Experience in Specman / System Verilog UVM.
Understanding simulation tools.
Experience in building test benches, evaluate coverage and debug simulation failures.

Requirements:
What We Need to See:

Bachelors degree in computer science or a related field, or equivalent experience.

Proven experience of at least 3 years in similar roles, emphasizing collaborative problem-solving.

Proficiency in Python programming.

Familiarity with developing modern Software Verification Systems, with a strong interest in algorithms.

Strong skills in implementing and debugging software, including experience working in a Linux environment.

Ways to Stand Out from the Crowd:

Understanding of the OCI/network model.

Knowledge of C/C++ programming.

Experience with Docker and Kubernetes.

A scripting background (e.g., Bash, Groovy).

Requirements:
Design Verification team lead - Peripheral IP Group (UVM) - (6047) We are looking for a handson Design Verification team lead to drive verification of nextgeneration wired/wireless peripheral subsystems that power Snapdragon platforms.
As a DV team lead in the Peripheral group, you will own verification of complex IPs and subsystems, define and execute a UVMbased verification strategy, and lead a small team of talented engineers to firsttimeright silicon. This role requires proven leadership experience and strong technical expertise.
This is a 5 days onsite position in Haifa.
What youll do: Define verification strategy, TEST plan, and coverage goals for complex peripheral IP and subsystem blocks
Architect, develop, and maintain UVMbased constrainedrandom verification environments
Lead daytoday activities of a small DV team: task planning, code and testplan reviews, mentoring, and technical guidance
Drive debug of complex issues across RTL, testbench, and system level, working closely with design, emulation and validation teams
Analyze and close functional and code coverage, drive quality metrics to tapeout criteria
Contribute to methodology and flow improvements across the Peripheral DV team Minimum qualifications: BSc/MSc in Electrical/Computer Engineering or related field
At least 7 years of handson verification experience using UVM and SystemVerilog
Proven experience in leading and managing a team
Strong background in digital design and SOC /IP architecture High technical proficiency in: UVM testbench architecture (agents, sequences, scoreboards, coverage)
Constrainedrandom, coveragedriven verification
Debugging complex failures in largescale regressions
Scripting ( Python / PERL /Tcl/shell) in a Unix / Linux environment Preferred qualifications: Experience with highspeed peripherals (e.g., USB, PCIe, Display, SerDes, or similar I/O IP)
Knowledge of lowpower, reset, and clockdomain interactions at IP/ SOC level
Familiarity with regression management, metrics, and signoff criteria
Experience working with global, crosssite teams

Requirements:
Bachelors degree in Electrical, Computer, or Software Engineering, or Computer Science.
Minimum 8 years of experience in system validation, verification, or integration across firmware and embedded software, including machine learning algorithm validation.
Demonstrated leadership in defining validation processes, methodologies, and quality standards.
Proficiency in Python and Bash scripting for automation and test development.
Experience with CI/CD pipelines, Git workflows, Docker, and cloud environments (AWS - advantage).
Strong analytical and debugging skills with the ability to drive system-level quality improvements.
Excellent communication skills with the ability to influence, coach, and align cross-functional teams.
Preferred Qualifications:
Experience with validation environments such as FPGA, emulation, RTL simulation, or post-silicon bring-up.
Background in embedded firmware practices (C/C++) and build systems (GNU Make, CMake).
Proven success in defect prevention initiatives and continuous improvement programs.
Familiarity with automotive standards (ISO 26262, ASIL-B, MISRA-C).
Hands-on experience with semiconductor test equipment (Advantest, Teradyne, or equivalent ATE platforms), including test program development, debug, and validation workflows.

Requirements:
B.Sc. in Electrical/Computer Engineering or equivalent.
5+ years of experience as a VLSI Verification Engineer.
Expertise in System-Verilog and UVM.
Strong software development skills and the ability to develop reusable verification components and utilities.
Strong organizational and planning skills, with the ability to prioritize and drive verification projects to completion.
Effective communicator with a structured, detail-oriented approach to problem-solving and collaboration.
Advantages:
Experience with Git, Python, code templating methods, and open-source verification workflows.
Familiarity with full-chip level aspects of VLSI verification (reset architecture and sequences, power domains and modes, etc.).
Experience in firmware verification, including emulation-based verification on FPGA.
Experience with formal verification or mixed-signal simulation.

Requirements:
5+ years of experience in RTL design or RTL verification.
Previous experience in networking - an advantage.
B.Sc. in Electrical Engineering or Computer Engineering.
A team player with good communication and interpersonal skills.

Requirements:
Senior Formal Verification engineer - Networking (6034) A unique opportunity to take part in building an R&D team for a global company.
We are seeking highly experienced and visionary formal Verification engineers to contribute to the development of advanced AI connectivity architectures and help define the formal verification methodology from the ground up.
Responsibilities:
Define and execute formal verification strategies and methodologies for complex SoCs, IPs, and networking architectures (Switches, NICs, SmartNICs).
Develop, implement, and maintain formal verification environments and TEST plans from concept to production.
Specify formal properties, assertions, and constraints using formal tools and SystemVerilog Assertions (SVA).
Own the formal verification environment, including setup, maintenance, and integration with simulation-based flows.
Collaborate closely with architecture, RTL, and design teams to identify corner cases, ensure functional correctness, and drive verification sign-off.
Act as a key contributor in shaping the formal verification infrastructure and methodology of the new Israeli site.
Qualifications:
B.Sc. in Computer Science or Computer Engineering.
8+ years of industry experience in formal verification.
Proven experience with JasperGold, VC Formal, or similar formal verification tools.
Demonstrated ownership and maintenance of formal verification environments.
Strong analytical and problem-solving skills.
Team player with excellent interpersonal and communication abilities.
Advantages:
Experience as a Verification engineer with practical knowledge of SystemVerilog and UVM methodology.
Familiarity with networking architectures and IPs (Switches, NICs, SmartNICs).
Experience integrating formal verification within broader project verification flows. 

Requirements:
Experienced Electrical Engineer with System Validation know how (SW, HW, FW)
B.Sc. in Electrical Engineering
5+ years of relevant experience
RF experience - mandatory
In depth knowledge of systems testing across domains (hardware, software and user specifications)
Knowledge of Linux fundamentals and scripting
Experience with testing development and monitoring tools
Excellent Communication and collaboration skills
Lab Hands-on and Integration experience with Software Embedded systems.
Willing to learn and work with embedded systems, Test equipment, Emulators, etc.
Proficient English - a big plus
Advantages
Experience working with FPGA, ASIC, RT
Experience working with test equipment such as SPECTRUM, SIGNAL GENERATOR, SCOP.

Requirements:
5+ years of relevant design verification experience
Proficiency in System Verilog UVM.

Requirements:
● B.Sc. in Electrical engineering.

● Specializing in Power Electronics - advantage

● At least 5+ years of experience as an Integration/SystemHW Engineer - Must

● Experience with multi-disciplinary systems - must

● The position requires strong hardware capabilities - Experience with lab equipment for hardware

bring-up and validations - must.

● Strong E2E system/product bring-up and validation capabilities.

● High documentation capability.

● Experience with automation scripts coding - advantage.

● Experience in EMI/EMC - advantage.

● Experience with wireless power charging - huge advantage.

Requirements:
Partner with development teams to define TEST requirements, review product specifications, and align on new feature implementations.
Design and execute comprehensive TEST coverage through both manual and automated testing strategies.
Identify software vulnerabilities, edge cases, and target areas for improvement.
Detect, reproduce, and document defects across development, service, and business processes.
Manage defect tracking and documentation within Azure DevOps.
Develop, maintain, and troubleshoot automation frameworks in accordance with evolving product requirements.
Establish and refine system testing procedures and best practices.

Requirements:
B.Sc. in Electrical Engineering or a related field.
6+ years of experience in ASIC/SoC Verification.
Experience leading verification planning and execution independently.
Preferred
Familiarity with RDMA, Ethernet, DDR or RISC-V.

Requirements:
6+ years of experience in digital logic design verification
Advanced knowledge of SystemVerilog and UVM
Strong debug skills both pre-silicon and in-lab
Preferred Qualifications
Scripting skills (Python, Perl, TCL, or shell)
Experience with system-level integration (AMBA, PCIe, SPI, I2C, JTAG, CPU)
Basic software knowledge (driver-level)
Basic design knowledge and familiarity with CDC concepts