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As a member of our CAD team, you will architect, develop, maintain and improve physical design verification (PDV) flows. The role requires you to work on flow and run-set development for various technology nodes and tool sets. Working alongside the CAD team, you will be collaborating with the custom digital/analog/mixed-signal design, physical design (PD) and chip integration teams. You will need to have a deep understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and/or modify existing ones. Also, you should have worked with Dummy Metal Fill generation and Design for Manufacturability (DFM) rules at different technologies.
Responsibilities
Develop, improve and maintain all aspects of physical verification flow and methodology
Coordinate the effort of validating flows, improving for custom checks and data generation
Work with the design and PD teams to facilitate the chip design process
Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs
Collaborate with tool vendors and foundries for PDK performance enhancements

As a Silicon Validation/Emulation Design Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators, as well as multiple ARM-based sub-systems. You will be a key contributor in our pre-silicon hardware validation efforts using Cadence Palladium emulation platforms, enabling early system integration and hardware validation. You will work closely with SoC architects, RTL designers, and verification engineers to ensure our designs are thoroughly validated before tape-out. You will help define the processes, methods, and tools for emulation environment development and debug of large complex SoCs.
If you enjoy a fast-paced and ambitious environment, collaborating with people across different functional areas, and thriving during crisis times, we encourage you to apply and join us!
Description
Building and maintaining Palladium emulation environments, including compile flows, netlist preparation, memory modeling, and clock/reset configurations.
System-level debug and root cause analysis of complex hardware issues on the emulation platform.
IP-level debug and validation, working closely with IP owners to isolate and resolve design issues.
Development and implementation of automation aids, flows, and scripts to improve Palladium build efficiency, debug turnaround, and platform utilization.
Performance profiling and optimization of emulation models to maximize execution speed.
Collaboration with multi-disciplinary groups to make sure emulation deliverables are on schedule and support critical program milestones.
Responsibilities
Own and maintain Palladium emulation build flows for SoC and subsystem-level models
Drive debug and triage of emulation model issues, working with RTL designers and verification engineers
Support system-level hardware validation efforts and hardware integration
Develop reusable debug methodologies and collateral to accelerate issue resolution
Optimize emulation model performance through compile tuning, partitioning strategies, and platform configuration
Thoroughly document flows, debug procedures, and best practices
Collaborate with cross-functional teams to define emulation requirements and support prototype hardware validation

We are seeking an experienced and hands-on engineering leader
to drive product quality, reliability, and performance across NPI, manufacturing, and the installed base. The role serves as a technical focal point for complex multidisciplinary issues, leading investigations, task forces, and improvement initiatives that enhance product quality , manufacturing readiness, and customer satisfaction.
What Will You Do?
Product Quality and Reliability:
Own product quality and reliability performance across NPI, manufacturing, and the installed base.
Define, monitor, and analyze quality metrics, reliability indicators, and field performance trends.
Consolidate quality and performance data from internal operations, contract manufacturers, and field systems into actionable insights and management dashboards.
Lead root-cause investigations and corrective/preventive actions (CAPA) for high-impact product and field issues.
Identify systemic issues, prioritize improvement opportunities, and drive cross-functional execution plans to improve product quality, reliability, and customer experience.
NPI, Manufacturing & Installed Base Support:
Drive quality and reliability readiness throughout NPI, validation, and production ramp-up activities.
Lead investigations into complex production, integration, and field failures involving multidisciplinary system interactions.
Partner with Manufacturing, Service, Operations, and Supply Chain teams to improve product stability, serviceability, and operational performance.
Drive implementation of calibration, alignment, validation, and test methodologies that improve quality, consistency, and manufacturing efficiency.
Support contract manufacturers and production teams in resolving critical technical and quality-related challenges.
Continuous Improvement & Change Management:
Lead engineering improvement initiatives based on production performance, customer feedback, reliability data, and field experience.
Drive product robustness, manufacturability, serviceability, and lifecycle performance improvements.
Own execution of Engineering Change Orders (ECOs), product structure management, and change implementation through CCB processes.
Lead periodic product performance reviews and drive closure of improvement actions across functions.

we are looking for a talented and experienced engineer to take part in the Emulation and Prototyping efforts for the companys core product. This position involves building a complex emulation environment from scratch, and collaborating with software, design, and verification teams. In this role, you will be leading emulation from A to Z and will have a critical impact on the company.

Responsibilities
Develop and build complex emulation models for coming generations of accelerators, including transactors like PCIe, SPI, and embedded CPUs
Work with the software, design, development, and verification teams to understand the functional and performance goals of the products design
Optimize the model for speed and capacity and develop debug abilities to support software and firmware teams
Work with software design and development teams to define and develop BFM, test bench, and checker tools
Review specifications and develop attributes, tests, and coverage plans for the emulation system

We are seeking a talented Program Manager to join our team. In this high-visibility, hands-on role, you will drive forward the development of our chip by managing the complete program lifecycle, from architecture to successful tapeout, ensuring deliverables meet scope, schedule, and quality requirements.

Responsibilities
Lead the planning, development and implementation process of cross-functional teams focused on product delivery.
Drive the execution of the hardware roadmap by managing the complete lifecycle from architecture definition to tapeout.
Partnering tightly with Architecture, RTL Design, and Design Verification (DV) leads to identify bottlenecks, track coverage metrics, and mitigate risks before they impact the tapeout schedule.
Define the core operational processes and modes of work for the entire HW group, building and refining the stage-gate reviews required to transition smoothly from architecture into implementation and verification.
Oversee project monitoring, reporting, and risk management, from initiation to delivery, addressing intergroup dependencies to ensure timely and successful completion.
Lead process and methodology improvements, proactively addressing issues to achieve business goals.

we are looking for a talented and experienced design manager to drive and help our group to get to the next era of computer architecture. In this position, you will design the critical parts of future chips. You will be involved in the full design cycle from architectural requirements into micro-architectural specs, implement key blocks in RTL, and participate in post-silicon activities.



Responsibilities
Be accountable for your team's milestones & timelines
Leading your team members and developing their abilities
Technology expert, building a knowledge base for the group
Work with various teams to drive execution (SW, Architecture, verification, BE, etc)
Devise execution indicators, monitor and report execution progress to enable prioritization and clear decision-making
Acquire the system Architecture and be part of the leading technical FE forum

we are looking for a talented and experienced Physical Design lead to take part in the physical design and help lead the companys BE activities . This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on our final product

Responsibilities


Lead blocks and sub systems execution from RTL to GDSII.
Clearly reflect status and execution metrics and help identify and solve execution bottlenecks.
Spec and define full floor plan, including pin placement, partitions, and power grid
Develop and validate high-performance, low-power clock network guidelines
Perform critical block-level place and route and create designs that meet PPA targets.
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations
Work with vendors on defining physical design methodologies and assist in flow development for chip

Come help lead the design and development of one of the most ambitious products at the forefront of compute technology!

Responsibilities
Lead a physical design team responsible for all stages of the physical design process-floor planning, placement, clock tree synthesis, routing, timing, and power optimization at both block and subsystem levels.
Mentor and guide a team of physical design engineers through all stages of the design flow.
Collaborate closely with project managers and other technical leads to ensure timely delivery and successful completion of projects.
Drive the technical direction of the physical design process to ensure efficient, high-quality outcomes.
Develop and implement best practices for physical design and continuous improvements of design workflows.
Optimize designs for performance, power, and area (PPA) to meet project goals.
Ensure compliance with DRC (design rule checking) and LVS (layout versus schematic) requirements. .
Drive timing analysis and closure, working closely with the RTL design team to resolve timing violations.

We are looking for an experienced, talented CPU ASIC front-end design expert and technical lead. In this role, you will take part in developing cutting-edge high performance best in class RISC-V CPU, from definition stage through planning stage and the development of new features while solving challenging implementation problems and ending in successful tape-out and product bring-up .




Responsibilities
Learn high performance RISC-V Arch and algorithms
Define and drive the design of advanced and super complexed blocks from micro-architecture phase to tape out.
Work closely with various teams to drive execution (SW, Architecture, verification, BE, FPGA, postSi etc)
Devise execution indicators and monitor and report execution progress to enable prioritization and clear decision making

we are looking for a talented and experienced engineer to participate in designing the next era of computer architecture. In this position you will take part in designing the critical parts of future chips. You will transform architectural requirements to micro-architectural specs, implement key blocks in RTL, and participate in post-silicon activities.

Responsibilities
Define and drive the design of advanced blocks from micro-architecture phase to netlist
Support timing and constraints definitions work closely with the BE team on timing and physical implementation efforts
Leading processes relating to power optimization
Technology expert, building a knowledge base for the group
Work with various teams to drive execution (SW, Architecture, verification, BE, etc)
Devise execution indicators and monitor and report execution progress to enable prioritization and clear decision making

we are looking for a talented and experienced engineer to participate in the physical design of the companys product for leading one of BE projects. This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on product architecture.

Responsibilities
Generate and analyze critical block- and chip-level static timing constraints
Spec and define full chip floor plan, including pin placement, partitions, and power grid
Develop and validate high-performance, low-power clock network guidelines
Perform critical block-level place and route and create designs that meet timing, area, and power constraints
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations
Work with vendors on defining physical design methodologies and assist in flow development for chip integration

We are seeking an exceptional Network Engineer to join the Vertical Verification Group. As a senior engineer, you will contribute to the Vertical Verification work, concentrating on validating and improving complex Ethernet and InfiniBand systems within our Data Center and HPC environments.

You will play a key role in testing advanced networking features, building complex customer-like topologies, and ensuring our products meet industry-leading benchmarks of performance, efficiency, and quality. You will collaborate closely with architects, software engineers, and hardware teams across NIC, HCA, switches, CPUs, and GPUs in a fast-paced and highly technical environment. This is an outstanding opportunity to join a highly skilled team and contribute significantly to groundbreaking technology!

What youll be doing:
Review architecture, build, and requirements for new networking features across Ethernet and InfiniBand portfolios.
Compose and build complex testbed topologies that emulate customer environments.
Implement, run and optimize integration test plans including functional, regression, and performance testing.
Identify, reproduce, and debug issues; work closely with R&D to drive root cause analysis and resolution.
Collaborate with automation teams.
Analyze and optimize network performance, latency, and efficiency.
Provide clear status updates, reports, and insights on system quality and performance.

We are now looking for a Chip Design Engineer to join our Switch Silicon team for Verification / Design roles. As a Chip Design Engineer in our Networking business unit, you'll join a group of passionate engineers to design, implement and verify the next generation state-of-the-art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What You'll Be Doing:

Work in a combined design and verification team which develops some of the switch silicon core units.

Micro-architecture for RTL and simulation environment planning for units and modules.

Design/Verify RTL units/blocks according to Arch. specifications under challenging constraints with high orientation to power, area, and performance.

Build reference models, verify, and simulate chip blocks/entities according to specifications.

RTL synthesis, timing, supporting verification, and silicon post TO activities.

Work closely with multiple teams within organizations such as Architecture, Full chip Micro-Architecture, BE, and FW.

Our Networking division is looking for an excellent Senior System Validation Engineer!

Our Networking division is a leading supplier of innovative end-to-end InfiniBand and Ethernet connectivity solutions and services for servers and storage. We offer market-leading solutions that include adapter cards, switches, cables, and software to support networking technologies. Our products optimize data center performance and deliver industry-leading bandwidth and scalability. In addition, we serve a wide range of markets including high-performance computing, enterprise, data centers, cloud computing, big data, and Web 2.0. We are constantly reinventing ourselves to stay ahead of the market and bring groundbreaking products and services to the industry.

What you'll be doing:

Test Verification and Validation (both HW and SW).

Maintain products quality by improving test stability, coverage, design, and manufacturing process in Mass Production.

Execute tests in different scopes such: as regression, performance degradation, functional, and security; report the progress of testing and provide summary reports of the activity.

Troubleshooting and streamlining/optimizing our testing procedures.

Support Mass production matters.

Debugging production bugs and solving them.