Participate in evaluation of future ASIC designs and general architecture for executing Googles data center networking roadmap: off-the-shelf components, vendor co-developments, custom designs, and chiplets.
Collaborate in developing new layer protocols for data center networking.
Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define performance hardware/software interfaces. Write micro architecture and design specifications
Requirements: Bachelor's degree in BSC, or a related field, or equivalent practical experience.
10 years of experience architecting networking ASICs from specification to production.
Experience working with design networking like: RDMA and or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience developing RTL for ASIC subsystems.
Experience in Cross-functional, micro-architecture, design, verification, logic synthesis, and timing closure.
Preferred qualifications:
Experience working with software teams optimizing the hardware/software interface.
Experience architecting networking switches, end points, and hardware offloads.
Experience in Transmission Control Protocol (TCP), IP, Ethernet, PCIE and Dynamic random-access memory (DRAM), Network on Chip (NoC) principles and protocols.
Experience in a procedural programming language (e.g. C++, Python, Go.).
Experience in estimating performance by analysis, modeling, and network simulation. Skilled in defining and driving performance test plans.
Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.
This position is open to all candidates.
